1. SPECIFICATIONS FOR LCD MONITOR General specifications LCD-PANEL : Active display area 15 inches or 15.1 inches diagonal 0.298 mm x 0.298 mm or 0.3 mm x0.3mm Pixel pitch 1024 x 768 RGB vertical stripe arrangement Pixel format Display Color : 6-bit, 262144 colors or 8-bit, 16.7 million colors External Controls : •...
LCD MONITOR DESCRIPTION The LCD MONITOR will contain an main board, an Inverter module, Adapter module and a keyboard. The main board will house the flat panel control logic, brightness control logic, DDC and DC-DC conversion to supply the appropriate power to the whole board and LCD panel. The Inverter module will drive the backlight of panel .
2. PRECAUTIONS AND NOTICES ASSEMBLY PRECAUTION (1) Please do not press or scratch LCD panel surface with anything hard. And do not soil LCD panel surface by touching with bare hands (Polarizer film, surface of LCD panel is easy to be flawed) In the LCD panel, the gap between two glass plates is kept perfectly even to maintain display characteristic and reliability.
3. OPERATING INSTRUCTIONS This procedure gives you instructions for installing and using the LM500 LCD monitor display. Position the display on the desired operation and plug the power cord into a convenient AC outlet. Three- wire power cord must be shielded and is provided as a safety precaution as it connects the chassis and cabinet to the electrical conduct ground.
4. ADJUSTMENT ADJUSTMENT CONDITIONS AND PRECAUTIONS Adjustments should be undertaken only on following function : contrast, brightness focus, clock, h-position, v- position, red, green, blue since 6500 color & 7800 color. ADJUSTMENT METHOD Press MENU button to activate OSD Menu or make a confirmation on desired function, Press Left/Right button to select the function or done the adjustment.
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switch the chroma-7120 to xyY mode With press “MODE” button Adjust the Contrast on OSD window until the Y measurement on chroma 7120 reached the value Y= 155 cd/m Press 78 on OSD window to save the adjustment result b. adjust 6500 color-temperature Set the Contrast of OSD function to 15, Brightness to –10 Switch the chroma-7120 to RGB-mode (with press “MODE”...
Clock adjustment Set the Chroma at pattern 63 (cross-talk pattern) or WIN98/95 shut-down mode (dot-pattern). Adjust until the vertical-shadow as wide as possible or no visible. This function is adjust the PLL divider of ADC to generate an accurate pixel clock Example : Hsyn = 31.5KHz Pixel freq.
5. CIRCUIT-DESCRIPTION THE DIFFERENT between LG-Panel & Samsung-Panel & CPT-Panel & Hannstar- Panel in ELECTRICAL Charateristic LG-Panel 1. Two CCFL (Cold Cathode Fluorescent Tube) 2. Single Pixel, 6 bit color (262144 colors) 3. Panel Vdd = 3.3V (in JP202 select 3.3V) Samsung-Panel 1.
and the other ACCESSORY when use different panel type should be change as following: 1). The INVERTER module for HANNSTAR panel part-number is 79AL15-6-S for LG panel the INVERTER part number is 79A-L15-1-S for CPT panel the INVERTER part number is 79A-L15-2-S 2).
SOFTWARE FLOW CHART Power-On Subrotine CHART POWER-ON START Initial MCU I/O, Interrupt vector & Ram Initial 1.POC (backlight counter) Check Eeprom is empty ? 2. Clr all mode value Check White-balance data(6500 & 7800) same with the backup data ? Check POC( backlight counter) data same with the backup data ? IF not same, overwrite the data with backup value.
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MAIN SUBROTINE LOOP Main loop start Process Power-saving status ( according to below flow-chart result) Check GMZAN IFM status .is change or not. And check Signal cable status ( cable not connected or not ) ** IFM is the register which measured the HSYN & Vsyn status Yes, IFM have change Wake-up GMZAN1 (because GMZAN1 was in...
6. A). Interface-Board Trouble-Shooting chart *Use the PC Win 98/95 white pattern, with some icon on it, and Change the Resolution to 640x480 60 Hz / 31 **NOTICE : The free-running freq. of our system is 48 KHz / 60 Hz, so we recommend to use another resolution to do trouble shooting, this trouble shooting is proceed with 640x480 @60Hz 31Khz NO SCREEN APPEAR OK, led in green-state...
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NG , no transition Measured PCLK(pin 44 from CN201) PVS,PHS (pin 40,38 from CN201) Check the bead-array & cap array(LP201•LP212 Is there have any transition? ,CP201•CP212 was cold solder or bad) Pclk around 31.25MHZ ,PVS=60.09Hz , PHS around 50.4KHz ??(for input signal=31K 60 Hz, and LED is green) Change PANEL to new one RE-do White-balance adjust...
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GMZAN1 BLOCK check Note : set the input signal ( PC or CHROMA) to 640x480 31k 60 hz Check input connector CN200 is loose?? Tighten CN200 cable & check relative circuit Measure R212,R211= 31K & 60 hz ? Measure R200,R201,R202 (RGB input ) had signal?? Screen is normal ? Measure U201 oscillator 50MHz is normal??
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PERIPHERAL PANEL BLOCK Note: “Panel vdd “ and “backlight on-off ” can be direct control by : GMZAN1 or MCU Some panel can direct control by GMZAN1 ,if the relative timing between panel-vdd and backlight on-off is short ( under 80 ms) , otherwise, will be control by MCU If J211 be connected, that means Panel-VDD control was by GMZAN1 ,otherwise by MCU( JP212) If J300 be connected, that means Backlight control was by GMZAN1 ,otherwise by MCU ( JP301) BUT Hannstar panel &...
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KEYBOARD BLOCK check Check U302 MCU pin 43,42,41,40,39 at Mechanical was stuck, Check ! High state(5V)? without press any key Replace Tact-switch SW105 at keyboard if still no work replace U302 MCU at main-board and Press power key and check U302 pin 43 check MCU relative reset circuit, and crystal = low (0V) ? Check U302 pin 38 (LED green) will have...
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POWER-BLOCK check *Note : the waving of U304 pin 2 can determined the power situation stable rectangle wave with equal duty, freq around 150K-158KHz that means all power of this interface board is in normal operation ,all status of 5V & 3.3V is normal working unstable rectangle wave without same duty, that means ABNORMAL operation was happened check 3.3V or 5V ,short-circuit or bad component rectangle wave with large spike &...
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III.ALL SCREEN HAS INTERFERENCES OR NOISE, CAN’T BE FIXED BY AUTO KEY ** NOTE: There is so many kind of interferences, 1). One is cause by some VGA-CARD that not meet VESA spec or power grounding too bad that influence our circuit 2).other is cause by external interferences, move the monitor far from electronic equipment.( rarely happened) Use DOT-pattern, or win98/99 shut-down...
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DOS MODE has jitter NOTE :the rule of doing AUTO-CONFIGURATION : must be a full-size screen, if the screen not full , the auto- configuration will fail. So in dos mode ,just set your “CLOCK” in OSD-MENU to zero or use some full screen edit file (ex: PE2, HE) and press “AUTO”...
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V. THE PANEL LUMINANCE WAS DOWN Use white pattern and resolution 1024x768 @ 60Hz , CHROMA 7120 measured the center of panel Set Contrast, brightness =maximal, RGB= 50 If Y can reach •180 cd/m2 that means Quit from OSD-screen, measured Y(luminance) The lamp still working well, so we just re-do the With chroma 7120, check Y= 210±10 CD/M2 ? white-balance process...
Inverter –MODULE Spec &Trouble Shooting Chart 6 B). In LM500 model , we use 3 kind of panel, each panel have their own inverter spec,therefore following spec is Hannstar-panel Inverter, LG-panel Inverter,CPT-panel Inverter offer from SAMPO-CORPORATION I.) TROUBLE SHOOTING OF HANNSTAR-INVERTER (part no : 79AL15-6-S) TYPE: L0048 FOR HANNSTAR 15”PANEL SAMPO CORPORATION TROUBLE SHOOTING OF HANNSTAR- INVERTER ( DIVTL0048-D21- -)
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SAMPO CORPORATION TROUBLE SHOOTING OF HANNSTAR- INVERTER ( DIVTL0048-D21- -) 5.FUNCTION SPECIFICATIONS: The data test with the set of SAMPO, and the test circuit is as below. SYMBOL MIN. TYP. MAX. UNIT REMARK ITEM Input voltage 10.8 13.2 Input current 1300 FOR 1 CCFL output current...
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8.PART LIST 8-1 COMPONENTS LIST: REF. PART NAME PART NUMBER DESCRIPTION SUPPLIER REMARK CON1 CONNECTOR VCNCP0015-EJSTA S5B-PH-SM3-TB • CON2,3 VCNCP0012-ZJSTA SM02(8.0)B.BHS-1-TB VCNCP0012-ZGLEA GL SM02(8.0)-WH2 GEAN-LEA RESISTOR VRMHNVA--303J-A SMD 0603 30K• 5% YAGEO • VRMHNVA--512J-A SMD 0603 5.1K• 5% YAGEO • VRMHNVA--272J-A SMD 0603 2.7K•...
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9. TROUBLE SHOOTING 9-1 NO POWER: CHECK ON FUSE TO CHANGE FAIL F1 Vin=12 F1= 1.5A/63Z TO CHANGE TO CHECK ON Q4&Q6 PASS FAIL L: Q4&Q3&D1 Vout = 8 V R: Q5&Q6&D2 TO CHECK ON L1&L2 PASS INPUT 9V TO L1 OR L2 TO CHANGE FAIL L: Q7&Q8&C12&PT1...
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9-2 HIGHT VOLTAGE PROTECTION: 1. SHORT R30 OPEN LOAD FAIL 2. TEST C14 INPUT POINT TO CHANGE ON VOLTAGE Vh=1400 ±150V rms PT1 OR PT2 PASS FUNCTION TEST OK! 9-3 OUTPUT CURRENT ABNORMALITY: FAIL 1 CHECK ON C6 FREQUNCY TO CHANGE ON C6 &CHIP&IC CPIP CHIP OR IC CHIP 2 OSCILLATOR FREQUNCY...
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9-4. ENBALE ABNORMALITY: IF ENBALE ABNORMALITY 1. TO CHECK IC PIN 9 TURN NO FAIL TO CHANGE ON Q1&Q2 HAVE 8.5 VOLTAGES FUNCTION TEST OK! PASS 9-5 DIMMING CONTROL ABNORMALITY: IF DIMMING ABNORMALITY TO FAIL TO CHANGE ON R1 OR R2 OR CHECK R1&R2&C6 HAVR BREAK PASS FUNCTION TEST OK!
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9-6 TRANSFORMER ABNORMALITY: FAIL IF TRANSFORMER ABNORMALITY TO TO CHANGE ON C3&C4 CHECK C3&C4 CHIP OUTLINE OR OR TRANSFORMER TRANSFORMER PASS FUNCTION TEST OK! 10. INSTRUMENTS FOR TEST: 1. DC POWER SUPPLY GPS-3030D 2. AC VTVM VT:-181E 3. DIGITAL MULTIMERTER MODEL-34401 4.
1.SAMPO PART NO .: L0023 ,AOC PART NO.: 79AL15-1-S 2.SCOPE : this is to specify the requirements of the subject parts used in L.G(LM151X4) 15 inch (2 C.C.F.L.) LCD monitor. 3.CONNECTOR PIN ASSIGMENT: 4-1. CON1: INPUT MODEL NO.: S5B-PH-SM3-TB SYMBOL DESCRIPTION Input voltage: 12V ON/OFF...
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5.FUNCTION SPECIFICATIONS: The data test with the set of SAMPO, and the test circuit is as below. ITEM SYMBOL MIN. TYP. MAX. UNIT REMARK Input voltage 10.8 13.2 Input current 1500 FOR 1 CCFL output current Iout LOAD:80K• adj:0v( min.) (min) FOR 1 CCFL Output current...
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8.PART LIST 8-1 COMPONENTS LIST: REF. PART NAME PART NUMBER DESCRIPTION SUPPLIER REMARK CON1 CONNECTOR VCNCP0015-EJSTA S5B-PH-SM3-TB • CON2,3 VCNCP0012-ZJSTA SM02(8.0)B.BHS-1-TB VCNCP0012-ZGLEA GL SM02(8.0)-WH2 GEAN-LEA R1,2 RESISTOR VRMCNV8--153F-A SMD 0805 15K• 1% YAGEO R3,4,21 • VRMCNV8--203F-A SMD 0805 20K• 1% YAGEO R5,6 •...
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9. TROUBLE SHOOTING 9-1 NO POWER: CHECK ON FUSE TO CHANGE FAIL F1 Vin=12 F1= 2.0A/63Z TO CHANGE L: Q4&Q3&D1 TO CHECK ON Q4&Q6 PASS FAIL R: Q5&Q6&D2 Vduot = 9 V TO CHECK ON L1&L2 PASS INPUT 9V TO L1 OR L2 TO CHANGE FAIL L: Q7&Q8&C12&PT1...
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9-2 HIGHT VOLTAGE PROTECTION: FAIL 1. SHORT R30 OPEN LOAD TO CHANGE ON 2. TEST C14 INPUT POINT PT1 OR PT2 VOLTAGE Vh=1500 ±150V rms PASS FUNCTION TEST OK! 9-3 OUTPUT CURRENT ABNORMALITY: FAIL 1. CHECK ON C6 FREQUNCY TO CHANGE ON C6 &CHIP&IC CPIP CHIP OR IC CHIP 2.
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9-4. ENABLE ABNORMALITY: IF ENBALE ABNORMALITY TO CHANGE ON Q1&Q2 1. TO CHECK IC PIN 9 TURN NO FAIL HAVE 12 VOLTAGES PASS FUNCTION TEST OK! 9-5 DIMMING CONTROL ABNORMALITY: IF DIMMING ABNORMALITY TO TO CHANGE ON R1 OR R2 OR FAIL CHECK R1&R2&C6 HAVR BREAK PASS...
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9-6 TRANSFORMER ABNORMALITY: IF TRANSFORMER ABNORMALITY TO TO CHANGE ON C3&C4 FAIL CHECK C3&C4 CHIP OUTLINE OR OR TRANSFORMER TRANSFORMER PASS FUNCTION TEST OK! 10. INSTRUMENTS FOR TEST: 1. DC POWER SUPPLY GPS-3030D 2. AC VTVM VT:-181E 3. DIGITAL MULTIMERTER MODEL-34401 4.
1.SAMPO PART NO .: L0026 , AOC PART NO. : 79AL15-2-S 2.SCOPE : this is to specify the requirements of the subject parts used in CHUNGHWA (CLAA150XA03) 15 inch (2 C.C.F.L.) LCD monitor. 3.CONNECTOR PIN ASSIGMENT: 4-1. CON1: INPUT MODEL NO.: S5B-PH-SM3-TB SYMBOL DESCRIPTION Input voltage: 12V...
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5.FUNCTION SPECIFICATIONS: The data test with the set of SAMPO, and the test circuit is as below. SYMBOL MIN. TYP. MAX. UNIT REMARK ITEM Input voltage 10.8 13.2 Input current 1500 FOR 1 CCFL output current Iout LOAD:80K• adj:0v( min.) (min) FOR 1 CCFL Output current...
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8.PART LIST 8-1 COMPONENTS LIST: REF. PART NAME PART NUMBER DESCRIPTION SUPPLIER REMARK CON1 CONNECTOR VCNCP0015-EJSTA S5B-PH-SM3-TB • CON2,3 VCNCP0012-ZJSTA SM02(8.0)B.BHS-1-TB VCNCP0012-ZGLEA GL SM02(8.0)-WH2 GEAN-LEA R1,2,19 RESISTOR VRMCNV8--133F-A SMD 0805 13K• 1% YAGEO R3,4, • VRMCNV8--273F-A SMD 0805 27K• 1% YAGEO •...
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9. TROUBLE SHOOTING 9-1 NO POWER: CHECK ON FUSE TO CHANGE FAIL F1 Vin=12 F1= 2.0A/63Z TO CHECK ON Q4&Q6 TO CHANGE PASS FAIL L: Q4&Q3&D1 Vduot = 9 V R: Q5&Q6&D2 TO CHECK ON L1&L2 PASS INPUT 9V TO L1 OR L2 TO CHANGE FAIL L: Q7&Q8&C12&PT1...
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9-2 HIGHT VOLTAGE PROTECTION: 1. SHORT R30 OPEN LOAD FAIL 2. TEST C14 INPUT POINT TO CHANGE ON VOLTAGE Vh=1750 ±150V rms PT1 OR PT2 PASS FUNCTION TEST OK! 9-3 OUTPUT CURRENT ABNORMALITY: FAIL 1. CHECK ON C6 FREQUNCY TO CHANGE ON C6 &CHIP&IC CPIP CHIP OR IC CHIP 2.
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9-4. ENABLE ABNORMALITY: IF ENBALE ABNORMALITY 1. TO CHECK IC PIN 9 TURN NO TO CHANGE ON Q1&Q2 FAIL HAVE 12 VOLTAGES FUNCTION TEST OK! PASS 9-5 DIMMING CONTROL ABNORMALITY: TO CHANGE ON R1 OR R2 OR IF DIMMING ABNORMALITY TO FAIL CHECK R1&R2&C6 HAVR BREAK PASS...
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9-6 TRANSFORMER ABNORMALITY: IF TRANSFORMER ABNORMALITY TO TO CHANGE ON C3&C4 FAIL CHECK C3&C4 CHIP OUTLINE OR OR TRANSFORMER TRANSFORMER FUNCTION TEST OK! PASS 10. INSTRUMENTS FOR TEST: 1. DC POWER SUPPLY GPS-3030D 2. AC VTVM VT:-181E 3. DIGITAL MULTIMERTER MODEL-34401 4.
6 C). ADAPTER-MODULE Trouble shooting chart The following spec & block-diagram is offer by LINEARITY –COMPANY, for Adapter-module part number : 80AL15-2-LI I.) Circuit Construction LAD4212BBL BRIDGE 90-265Vac TRANSFORMER SMOTH RECTIFIER RECTIFIER FILTER INPUT & FILTER CIRCUITS OUTPUT CAPACITANCES OVER VOLTAGE PROTECTION VOLTAGE...
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II. ADAPTER MODULE TROUBLE SHOOTING CHART Check Fuse (F01) is broken or destroyed ? Check all PAD on PCB board was short circuit or cold solder? BD01 broken Check the polar “+” of BRIDGE Rectifier CKT ( BD01) have DC Voltage around = 1.414 * AC Input voltage Check IC3842 pin 7 have a voltage ? a).IC3842 broken...
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IV. ADAPTER BOM LIST ( PART no. 80AL15-2-LI) Location Description Location Description Location Description R 01 CFR 1 M• C 01 SC ×2 0.22• U 01 SCR IC R 03 MOFR 91K C 02 EC 120• U 02 UC3842BN R 04 CFR 510K C 04 EC 47•...
GMZAN1 The gmZAN1device utilizes Genesis’ patented third-generation Advanced Image Magnification technology as well as a proven integrated ADC/PLL to provide excellent image quality within a cost effective SVGA/XGA LCD monitor solution. As a pin-compatible replacement for the gmB120, the gmZAN1 incorporates all of the gmB120 features plus many enhanced features;...
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1.3 Pin Description Unless otherwise stated, unused input pins must be tied to ground, and unused output pins left open. Table 1 : Analog-to-Digital Converter PIN # Name I/O Description Digital power for ADC encoding logic. Must be bypassed with 0.1uF capacitor to ADC_VDD2 pin 78 (ADC_GND2) Digital GND for ADC encoding logic.
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Table 2 : Host Interface (HIF) / External On-Screen Display PIN # Name I/O Description Host Frame Sync. Frames the packet on the serial channel. Clock signal input for the 3-wire serial communication. HCLK Data signal for the 3-wire serial communication. HDATA Resets the gmZAN1 chip to a known state when low.
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Table 3 : Clock Recovery / Time Base Conversion PIN # Name I/O Description Digital power for Destination DDS (direct digital synthesizer). Must be bypassed DVDD with a 0.1uF capacitor to digital ground plane. Analog ground for Destination DDS DAC. Must be directly connected to the DAC_DGNDA analog system ground plane.
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Description PIN # Name 2pxl/clk 2pxl/clk 1pxl/clk 1pxl/clk 8bit 6-bit 8-bit 6-bit TFT PdispE This output provides a panel display enable signal that is active when flat panel data is valid. This output provides the panel line clock signal. This output provides the frame start signal. PCLKA This output is used to drive the flat panel shift clock.
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1.4 System-level Block Diagram CVDD ADC_VDD RVDDA gmZAN1 Core ADC_GND RGNDA Blue TCLK Green SVDDA RVDDA Hsync To Clock SGNDA Vsync Generator DVDDA DGNDA R+,G+,B+ Even Data On-Screen OSD-FSW OSD-FSW PCLKA Display OSD-CLK Controller OSD-HREF OSD-VREF PDISPE Odd Data MPU with HCLK EPROM +12V...
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1.5 Operating Modes The Source Clock (also called SCLK in this document) and the Panel Clock are defined as follows: The Source Clock is the sample clock regenerated from the input Hsync timing (called clock recovery) by SCLK DDS (direct digital synthesis) and the PLL. The Panel Clock is the timing clock for panel data at the single pixel per clock rate.
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1.5.4 Downscaling Panel Clock frequency < Source Clock frequency Panel Hsync frequency < Input Hsync frequency Panel Vsync frequency = Input Vsync frequency This mode is used when the input resolution is greater than the panel resolution, to provide enough of a display to enable the user to recover to a supported resolution.
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2. FUNCTIONAL DESCRIPTION Figure 3 below shows the main functional blocks inside the gmZAN1 2.1 Overall Architecture Figure 3. Block Diagram for gmZAN1 On-Screen Display Control Analog Triple Source Scaling Gamma Panel Timing Engine Control Timing Panel Measurement (CLUT) Control / Generation Dither Pixel...
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The SCLK frequency (1/SCLK period) can be set to the range of 10-to-135 MHz. Using the DDS (direct digital synthesis) technology the clock recovery circuit can generate any SCLK clock frequency within this range. The pixel clock (DCLK or destination clock) is used to drive a panel when the panel clock is different from SCLK (or SCLK/2).
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The table below summarizes the characteristics of the clock recovery circuit. Table 7. Clock Recovery Characteristics Minimum Typical Maximum SCLK Frequency 10MHz 135 MHz Sampling Phase Adjustment 0.5 ns/step, 64 steps Patented digital clock synthesis technology makes the gmZAN1 clock circuits very immune to temperature/voltage drift.
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2.3 Analog-to-Digital Converter 2.3.1 Pin Connection The RGB signals are to be connected to the gmZAN1 chip as described in Table 8 and Table 9. Table 8. Pin Connection for RGB Input with Hsync/Vsync GmZAN1 Pin Name (Pin Number) CRT Signal Name Red+(#95) Red- (#94) N/A (Tie to Analog GND for Red on the board)
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2.3.2 Sync. Signal Support The gmZAN1 chip supports digital separate sync (Hsync/Vsync), digital composite sync, and analog composite sync (also known as sync-on-green). All sync types are supported without external sync separation / extraction circuits. Digital Composite Sync The types of digital composite sync inputs supported are: OR/AND type: No Csync pulses toggling during the vertical sync period XOR type: Csync polarity changes during the vertical sync period The gmZan1 provides enough sync status information for the firmware to detect the digital composite sync type.
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The display start/end registers store the first and the last pixels/lines of the last frame that have RGB data above a programmed threshold. The reference point of the STM block is the same as that of the source timing generator (STG) block: The first pixel: the pixel whose SCLK rising edge sees the transition of the HSYNC polarity from low to high.
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2.5.1 Scaling Filter The gmZAN1 scaling filter uses an advanced adaptive scaling technique proprietary to Genesis Microchip Inc. and provides high quality scaling of real time video and graphics images. This is Genesis’ third generation scaling technology that benefits from the expertise and feedback gained by supporting a wide range of solutions and applications.
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Table 13. gmZAN1 TFT Panel Interface Timing Signal Name Typical Unit Period 16.67 2048 lines Frequency Front porch 2048 lines Back porch 2048 lines Pulse width 2048 lines PdispE Panel height 2048 lines Disp. Start from VS t6 2048 lines PVS set up tp PHS 2048 PCLK *1...
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Figure 7. timing Diagrams of the TFT Panel Interface (One pixel per clock) (a) Vertical size in TFT (b) Vsync width and display position in TFT RGBs (c) Horizontal size in TFT PCLK RGB data from data paths (d) Hsync width in TFT Panel Background Color Displayed...
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Figure 8. Data latch timing of the TFT Panel Interface (a) Two pixel per clock mode in TFT PCLK R2,(N:0) R4,(N:0) R0,(N:0) G0,(N:0) G2,(N:0) B2,(N:0) B0,(N:0) R1,(N:0) R3,(N:0) G1,(N:0) G3,(N:0) (b) One pixel per clock mode in TFT B1,(N:0) B3,(N:0) PCLK R(n:0 G(n:0...
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2.6.2.1 State 0 (Power Off) The Pbias signal and Ppower signal are low (inactive). The panel controls and data are forced low. This is the final state in the power down sequence. PM is kept in state 0 until the panel is enabled. 2.6.2.2 State 1 (Power On) Intermediate step 1.
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2.6.3 Panel Interface Drive Strength As mentioned previously, the gmZAN1 has programmable output pads for the TFT panel interface. Three groups of panel interface pads (panel clock, data, and control) are independently controllable and are programmed using API calls. See the API reference manual for details. Table 14.
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2.7.1 Serial Communication Protocol In the serial communication between the microcontroller and the gmZAN1, the microcontroller always acts as an initiator while the gmZAN1 is always the target. The following timing diagram describes the protocol of the serial channel of the gmZAN1 chip. Figure 10.
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Table 15 summarizes the serial channel specification of the gmZAN1. Refer to Figure 10 for the timing parameter definition. Table 15. gmZAN1 Serial Channel Specification Parameter Min. Typ. Max. Word Size (Instruction and Data) 12 bits HCLK low to HFS high (t1) 100 ns HFS low to HCLK inactive (t2) 100 ns...
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2.8.1 OSD Color Map Both the internal and external OSD display use a 16 location SRAM block for the color programming. Each color location is a twelve-bit value that defines the upper four bits of each of the 8 bit Red, Blue and Green color components as follows: D3:0 Blue;...
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To improve the appearance and make it easy to find the OSD window on the screen, the user may select optional shadowing (3D effect). The “Shadow” feature operates in the same manner as in the B120; that is, it produces a region of half intensity (scaler data) pixels of the same width and height as the OSD window, but offset to the right and down by 8 pixels/lines (the border width setting has no effect).
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3. ELECTRICAL CHARACTERISTICS Table 20. Absolute Ratings Parameter Min. Typ. Max. Note PVDD 5.6 volts CVDD 5.6 volts Vss-0.5 volt Vcc+0.5V Operating temperature 0 degree C 70 degree C Storage temperature -65 degree C 150 degree C Maximum power consumption Table 21.
POWER SYSTEM AND CONSUMPTION CURRENT ADAPTER MODULE INVERTER MODULE Input AC 110V, 60Hz/240V, 50Hz Input DC 12V Output AC 1500V/30K-50KHz Output DC 12V 3.5A Current 9mA Main board power system LM2596S-5, 12V to 5V (3A SPEC) To CPU, Eeprom, 24c21, control-inverter-on.off 860mA when Cable not Connected 841mA when Normal operation AIC1084, 5V to 3.3V (5A SPEC)