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6. SYSTEM EXPLANATION
1. PCB CONSTRUCTION
This digital reverb DRV-1000 is designed very compact,
and consists of following 3 PCBs.
1) Analog PCB KLM-840
As shown in the circuit diagram, the main circuitries are;
PRE-EMPHASIS, DE-EMPHASIS,
LOW PASS FILTER,
SAMPLE/HOLD, COMPUTER and DAC.
2) Digital PCB KLM-839
Process vocal data by the custom gate array.
3) Power PCB KLM-843
Supply ±5V. to the analog circuit, and +5V. to the digital
circuit.
2. REVERB PATTERN/TIME SETTINGS
PATTERN
NUMBER
PATTERN
TIME NUMBER
|
2
3
4
5
6
7
8
1
SMALL HALL
0.7*
1.2*
1.8*
2.4*
3.0*
3.6*
4.4*
5.2*
2
LARGE HALL
1.2*
1.6*
2.1*
2.6*
3.4*
4.6*
7.0*
10.0*
3
ROOM
0.20*
0.23*
0.26*
0.29*
0.31*
0.34*
0.37*
0.40*
4
Garage
0.7*
0.9*
1.2*
1.5*
1.8*
2.2*
2.6s
3.2*
S
VOCAL PLATE
0.7*
1.0*
1.3*
1.7*
2.0*
2.3*
2.7*
3.4*
6
INSTRUMENTS PLATE
0.7*
0.9*
1.1*
1.3*
1.6*
1.8*
2.1*
2.6*
7
GATED REVERB
150m*
180m*
220m*
260m*
290m*
320ms
360m*
400ms
a
REVERSE
ISOrrw
180m*
210m*
240m*
270m*
290m*
320m*
350m*
Pattern/time data indicated in above table are stored in
a 256Kbit EPROM on KLM-839, and by the combinations
of the patterns (1 - 8), time (1-8) and H. DAMP ON/OFF,
the upper address is determined and accordingly 128 ways
of the effects will be gained in total.
Following is setting logic of the patterns and the time swit¬
ches against the address of the EPROM.
PI
P2
P3
P4
P5
P6
P7
P8
T1
T2
T3
T4
T5
T6
T7
T8
A 8
L
L
L
L
L
'L
L
L
L
H
L
H
L
H
L
H
A 9
L
L
L
L
L
L
L
L
L
L
H
H
u
l
H
H
A10
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
All
L
H
L
H
L
H
L
H
L
L
L
L
L
L
L
~
A12
L
L
H
H
L
L
H
H
L
L
L
L
L
L
L
L
A13
L
L
L
L
H
H
H
H
L
L
L
L
L
~ ~
A14
H
H
H
H
H
H
H
H
H
H
H
H
~hT H
H
Note: 1
P = Pattern, T = Time
2 When the H. DAMP is on, A14 must be all "L" re¬
gardless of the switch settings.
3 At the LONG ON setting, A8 - A10 except PAT¬
TERN 7 & 8 (with GATED REVERB and RE¬
VERB) should be "H".
3. OUTLINE OF GATE ARRAY
The DRV-1000 has adopted two newly developed GATE
ARRAYS. We give an explanation on the each array here.
1) MB652109
This gate array consists of SAR (Successive Approximation
Resistor), reverbration process circuit (resistors of 24 bit,
adder, multiplier of 24 bit x 6 bit) and BUS circuit for
outer memory.
Main function here is calculation of vocal data.
Following are the functions of each terminal.
TERMINAL NAME
INPUT/
OUTPUT
FUNCTION
DAI~ DAIS
0
DATA OUTPUT TERMINAL
OUTPUT to OAC
COUT
1
DATA INPUT TERMINAL
INPUT from the comparator
eoc
0
Selection/control signal output of A/D terms or D/A terms
SEEC
1
Internal Selector terminal
TEST:
Mode for direct output of A/D data to D/A
NORMAL: To output internally processed data during the
D/A period according to the EOC signal
OR1 ~ DR24
I/O
IN/OUTPUT terminal for 24 bit vocal data, and the data bus
among the ORAMs (IC13-181 on KLM-839.
LTAC - SEDC
1
Input terminal of control signals for calculation sent from
MB654122
2) MB654122
This LSI holds a function to output all the necessary tim¬
ing/control signals for calculation in accordance with the
panel operations such as PATTERN, TIME settings and etc.
The functions of each terminal are as follows.
TERMINAL NAME
INPUT/
OUTPUT
FUNCTION
x 1
1
Generation of 22MHz SYSTEM CLOCK by operating the crystal
x2
0
oscillator
SHAD, SHL, SHR
0
Output the control signals for sample/hold
LTAC~SEDC
0
8 patterns x 8 times x 2 H. DAMP ON/OFF
Output terminal for process patterns
DRAG ~ DRA7
0
Address output terminal for DRAM
RAS, CAS, WE, OE
0
Control signal output terminal in DRAM READ/WRITE
MEOO ~ MED7
(
Input terminal for panel switch data
ME AO - MEA7
0
Address output terminal to EPROM
RESE
1
Input terminal for internal counter reset
4. MEMORY CONSTRUCTION
To memorize 24 bit data for operation, 6 Dynamic RAMs
of 16K x 4 bit compose the memory.
—12 —
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