LG 47LW570Y Service Manual page 51

GP3 Backend block diagram (PG)
DDR3 SDRAM
DDR3 SDRAM
- 1Gbit (x16)
- 1Gbit (x16)
- 800MHz
- 800MHz
+12VD
DC-DC Converter
DC-DC Converter
(AOZ1072AI)
(AOZ1072AI)
+12VD
DC-DC Converter
DC-DC Converter
(AOZ1072AI)
(AOZ1072AI)
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Only for training and service purposes
DDR1_A[12:0]/
BA[2:0]/CLK/CKE
DDR1_DATA[15:0]
+3.3V_FRC
Quad-link LVDS(@74.25MHz)
+1.26V_FRC
51Pin LVDS output
XTAL_IN
XTAL_OUT
URSA5
(0xB4)
SPI_DI
SPI_DO/CK/CS
41Pin LVDS output
BCM35230
LVDS data from
X-Tal
(24.75Mhz)
Main IC
( BCM35230 )
SPI FLASH
SPI FLASH
(4Mbit)
(4Mbit)
0X98
0X98
+1.5V
LDO Regulator
LDO Regulator
(AP7173-SPG-13)
(AP7173-SPG-13)
+3.3VD
LGE Internal Use Only