Table of Contents
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NAND FLASH MEMORY 8Gbit
+3.3V_Normal
IC102
TC58DVG3S0ETA00
NC_1
NC_28
1
NAND_8Gbit
48
NC_2
NC_27
2
47
NC_3
NC_26
3
46
NC_4
NC_25
4
45
NC_5
I/O8
5
44
16Gbit
NC_6
I/O7
R149
0
6
43
RY/BY
I/O6
NAND_RBb
7
42
RE
I/O5
NAND_REb
8
41
CE
NC_24
NAND_CEb
9
40
16Gbit
NC_7
PSL
R148
0
10
39
NAND_CEb2
NC_8
NC_23
C102
11
38
4700pF
VCC_1
VCC_2
12
37
C101
VSS_1
VSS_2
0.1uF
13
36
NC_9
NC_22
14
35
NC_10
NC_21
15
34
CLE
NC_20
NAND_CLE
16
33
ALE
I/O4
NAND_ALE
17
32
WE
I/O3
NAND_WEb
18
31
WP
I/O2
Write Protection
+3.3V_Normal
19
30
NC_11
I/O1
- High : Normal Operation
20
29
- Low
: Write Protection
NC_12
NC_19
21
28
NC_13
NC_18
22
27
FLASH_WP
NC_14
NC_17
23
26
NC_15
NC_16
24
25
IC101
LGE35230(BCM35230KFSBG)
BCM_WITHOUT_CAP
B5
AE27
HDMI_CLK-
HDMI0_CLKN
TXOUT0_L0N
C5
AE28
HDMI_CLK+
HDMI0_CLKP
TXOUT0_L0P
AF27
TXOUT0_L1N
A4
AF28
HDMI_RX0-
HDMI0_D0N
TXOUT0_L1P
B4
AG27
HDMI_RX0+
HDMI0_D0P
TXOUT0_L2N
AG28
TXOUT0_L2P
+3.3V_Normal
A3
AE26
HDMI_RX1-
HDMI0_D1N
TXCLK_LN
B3
AF26
HDMI_RX1+
HDMI0_D1P
TXCLK_LP
AH27
TXOUT0_L3N
A2
AG26
HDMI_RX2-
HDMI0_D2N
TXOUT0_L3P
R101
R105
R104
R195
B2
AF25
4.7K
4.7K
4.7K
4.7K
HDMI_RX2+
HDMI0_D2P
TXOUT0_L4N
AE25
TXOUT0_L4P
W2
CEC
AH26
TXOUT0_U0N
V4
AG25
DDC0_SCL
TXOUT0_U0P
W4
AE24
DDC0_SDA
TXOUT0_U1N
AD24
TXOUT0_U1P
V3
AH25
HDMI0_HTPLG_IN
TXOUT0_U2N
V2
AF24
HDMI0_HTPLG_OUT
TXOUT0_U2P
AE23
TXCLK_UN
D13
AD23
HDMI_ARC
HDMI0_ARC
TXCLK_UP
E6
AG24
HDMI0_RESREF
TXOUT0_U3N
AF23
TXOUT0_U3P
R106
AC22
3K
TXOUT0_U4N
AD22
TXOUT0_U4P
AG23
TXOUT1_L0N
AH23
TXOUT1_L0P
AE22
TXOUT1_L1N
AE21
TXOUT1_L1P
AF22
TXOUT1_L2N
AH22
TXOUT1_L2P
AG22
TXCLK1_LN
AF21
TXCLK1_LP
AG21
TXOUT1_L3N
AF20
TXOUT1_L3P
AD21
TXOUT1_L4N
AC21
TXOUT1_L4P
AG20
TXOUT1_U0N
AH20
TXOUT1_U0P
AD19
TXOUT1_U1N
AE19
TXOUT1_U1P
AF19
TXOUT1_U2N
AH19
TXOUT1_U2P
AE18
TXCLK1_UN
AD18
TXCLK1_UP
AG19
TXOUT1_U3N
AF18
TXOUT1_U3P
AG18
TXOUT1_U4N
AF17
TXOUT1_U4P
AC18
LT0VCAL_MONITOR
AH16
GPIO_BL_ON
AG16
BL_PWM/GPIO
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
16Gbit
IC102-*1
TH58DVG4S0ETA20
NC_1
NC_26
1
48
DEV_NAND_16Gbit
NC_2
NC_25
2
47
NC_3
NC_24
3
46
NC_4
NC_23
4
45
NAND_DATA[0-7]
NC_5
I/O8
5
44
NAND_DATA[7]
RY/BY2
I/O7
6
43
NAND_DATA[6]
RY/BY1
I/O6
7
42
NAND_DATA[5]
RE
I/O5
8
41
NAND_DATA[4]
CE1
NC_22
9
40
CE2
PSL
16Gbit
10
39
0
R151
NC_6
NC_21
11
38
VCC_1
VCC_2
12
37
+3.3V_Normal
VSS_1
VSS_2
13
36
C104
10uF
10V
NC_7
NC_20
14
35
C103
NC_8
NC_19
15
34
0.1uF
CLE
NC_18
16
33
ALE
I/O4
17
32
NAND_DATA[3]
WE
I/O3
18
31
NAND_DATA[2]
WP
I/O2
19
30
NAND_DATA[1]
NC_9
I/O1
20
29
NAND_DATA[0]
NC_10
NC_17
21
28
NC_11
NC_16
22
27
NC_12
NC_15
23
26
NC_13
NC_14
24
25
+3.3V_Normal
R196
10K
RGB_DDC_SDA
TXB4P
Q101
BSS83
TXB4N
TXB3P
TXB3N
C118
TXBCLKP
0.1uF
16V
TXBCLKN
TXB2P
TXB2N
+3.3V_Normal
TXB1P
TXB1N
TXB0P
R198
TXB0N
10K
RGB_DDC_SCL
TXA4P
TXA4N
Q102
BSS83
TXA3P
TXA3N
TXACLKP
C119
TXACLKN
0.1uF
16V
TXA2P
TXA2N
TXA1P
TXA1N
+3.3V_Normal
TXA0P
TXA0N
BBS CONNECT
DEBUG_BBS
TXD4P
+3.3V_Normal
P101
TXD4N
SDA0_3.3V
TJC2508-4A
TXD3P
SCL0_3.3V
TXD3N
TXDCLKP
VCC
SCL2_3.3V
1
TXDCLKN
R109
R110
C106
1.5K
SDA2_3.3V
4.7uF
1.5K
TXD2P
SCL
R199
22
TXD2N
2
R197
22
TXD1P
TXD1N
SDA
3
TXD0P
TXD0N
GND
4
DVB_S
DVB_S Option: apply EU Satellite model
TXC4P
TXC4N
TXC3P
TXC3N
FOR HDMI STANDARD
TXCCLKP
APPLY ONLY WHEN CONNECT TO PULL-UP GPIO
TXCCLKN
TXC2P
TXC2N
TXC1P
TXC1N
TXC0P
TXC0N
+3.3V_Normal
R194
2.7K
R108
10K
A_DIM
C105
2.2uF
10V
Boot ROM Device Select - (FA4,FAD7,FAD2,FAD1)
+3.3V_Normal
0000: ST Micro M25P or compatible Serial Flash
0010: 8-bit 512Mbit 512B page SLC NAND Flash devices
0100: 8-bit 128, 256Mbit 512B page SLC NAND Flash devices
0110: 8-bit 1Gbit 2KB page SLC NAND Flash devices
R113
R117
R122
R127
10K
10K
10K
10K
1000: 8-bit 2Gbit, 4Gbit, 8Gbit 2KB page SLC NAND Flash devices
OPT
OPT
1010: 8-bit 16Gbit, 32Gbit 4KB page SLC NAND Flash devices (O)
CI_ADDR[4]
0001: 8-bit 8/16/32Gbit 2KB page MLC NAND Flash devices
NAND_DATA[7]
0011: 8-bit 16/32Gbit 4KB page MLC NAND Flash devices
0101: 8-bit 32Gbit 8KB page MLC NAND Flash devices
NAND_DATA[2]
0111: 3B dual IO Serial Flash
NAND_DATA[1]
1001: BB dual IO Serial Flash
R114
R118
R123
R128
1011: fast Serail Flash > 50Mhz
10K
10K
10K
10K
1100: OneNAND Flash (always 16-bit)
OPT
OPT
1110: Reserved
1101, 1111: Reserved
NAND ECC (FA3, FA2, FALE)
+3.3V_Normal
R111
R115
R119
10K
10K
10K
000 = ECC disabled
OPT
OPT
CI_ADDR[3]
001 = ECC 1-bit repair
010 = ECC 4-bit BCH (O)
CI_ADDR[2]
011 = ECC 8-bit BCH, 27 byte spare
NAND_ALE
100 = ECC 12-bit BCH, 27 byte spare
101 = ECC 8-bit BCH, 16 byte spare
R112
R116
R120
10K
10K
10K
110, 111 = Reservedd
OPT
DUAL COMPONENT
IC102
1ST : EAN61000101
2ND : T-TH58DVG4S0ETA20
IC102-*1
IC101
LGE35230(BCM35230KFSBG)
BCM_WITHOUT_CAP
AG6
AB1
54MHz_XTAL_P
TVM_XTALIN
FAD_7
AB3
FAD_6
AF6
AC1
54MHz_XTAL_N
TVM_XTALOUT
FAD_5
AC2
FAD_4
AC3
FAD_3
V5
AD2
LNB_INT
IRRXDA
FAD_2
AD3
FAD_1
AE2
FAD_0
AB4
FP_IN0
Y4
FP_IN1
AG1
FALE
AA4
AF1
SPARE_ADC1
FCEB_0
Y5
AC5
SPARE_ADC2
FCEB_1
AE6
FCEB_2
AB2
AG5
SC_ID
FS_IN1
FCEB_3
AB5
FS_IN2
AF3
NFWPB
U3
AG2
VGA_SDA
FWE
U2
AE3
VGA_SCL
FRD
AA5
FRDYB
Y2
BCM_RX
RDA
R121
R126
R129
R131
Y1
AF2
TDA
FA_0
1.2K
1.2K
1.2K
1.2K
BCM_TX
AE1
FA_1
R135
33
AA3
AC4
BSCDATAA
FA_2
R136
33
AA2
AD5
BSCCLKA
FA_3
AD4
FA_4
H3
AE4
RDB/GPIO
FA_5
H2
AE5
TDB/GPIO
FA_6
AD6
FA_7
H4
AH3
BSC_S_SCL
FA_8
H5
AF4
BSC_S_SDA
FA_9
AH4
+3.3V_Normal
FA_10
C107
C108
C109
C110
AG4
FA_11
33pF
33pF
33pF
33pF
F25
AF5
R141
4.7K
50V
50V
50V
50V
NMIB
FA_12
AG3
DVB_S
FA_13
W5
AH2
PCM_5V_CTL
POWER_CTRL
FA_14
AH5
FA_15
5V_HDMI_1
OPT
U5
R142
22
AON_HSYNC
5V_HDMI_2
U4
R143
22
AON_VSYNC
OPT
AD15
5V_HDMI_3
TRSTB
OPT
W3
AF14
R144
22
AON_GPIO_36
TDI/GPIO
5V_HDMI_4
W1
AH14
R130
R145
22
AON_GPIO_37
TDO
OPT
2K
AD14
OPT
+3.3V_Normal
TMS/GPIO
AB6
AG14
AON_RESETOUTB
TCK/GPIO
Y6
AC16
R132
4.7K
TVM_BYPASS
DINT/GPIO
R139
0
SRST
Y3
AH7
+3.3V_Normal
SOC_RESET
RESETB
AVS_VFB
G24
AG7
RESETOUTB
AVS_VSENSE
AD7
R124
AVS_RESETB
1K
J6
AF7
TMODE
AVS_NDRIVE_1
OPT
W6
AH8
TESTEN
AVS_PDRIVE_1
+3.3V_Normal
R125
1K
F7
C6
C111
0.01uF
VDAC_VREG
VDAC_1
E7
D7
C112
0.1uF
VDAC_RBIAS
VDAC_2
R140
560
1%
BCM REFRENCE is 562ohm
Strap Setting
+3.3V_Normal
R154
R157
R160
10K
10K
10K
OPT
OPT
OPT
R155
R158
R161
10K
10K
10K
NAND_DATA[0]:
0: System is LITTLE endian (O)
1: System is BIG endian
CI_ADDR[7]:
0: Disable EDID automatic Downloading from Flash (O)
1: Enable EDID automatic Downloading from Flash
NAND_DATA[6] :
0: Disable OSC clock output on chip Pin (O)
1: Enable OSC clock output on chip pin.
CI_ADDR[6]:
0: Host MIPS run at 500 MHz (O)
1: Host MIPS run at 250 MHz
NAND_CLE:
0: Differential Oscillators TVM not bypassed (O)
1: Differential Oscillators TVM bypassed
NAND_DATA[4]:
0: 27MHz TVM Crystal Frequency
1: 54MHz TVM Crystal Frequency (O)
NAND_DATA[0-7]
NAND_DATA[7]
NAND_DATA[6]
NAND_DATA[5]
NAND_DATA[4]
NAND_DATA[3]
NAND_DATA[2]
NAND_DATA[1]
NAND_DATA[0]
NAND_ALE
NAND_CEb
NAND_CEb2
/CI_CE1
/CI_CE2
FLASH_WP
NAND_WEb
NAND_REb
/PCM_WAIT
CI_ADDR[2-14]
NAND_CLE
NAND_RBb
CI_ADDR[2]
CI_ADDR[3]
CI_ADDR[4]
CI_ADDR[5]
CI_ADDR[6]
CI_ADDR[7]
CI_ADDR[8]
CI_ADDR[9]
CI_ADDR[10]
CI_ADDR[11]
CI_ADDR[12]
+3.3V_Normal
CI_ADDR[13]
CI_ADDR[14]
R146 10K
R147
R150
R153
R156
R159
R162
R166
1K
1K
1K
1K
1K
1K
1K
R163
1K
SRST
DTV/MNT_V_OUT
R164
R167
R170
R175
R177
R179
R181
R183
R187
R192
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
OPT
OPT
OPT
OPT
OPT
OPT
OPT
NAND_DATA[0]
CI_ADDR[7]
NAND_DATA[6]
CI_ADDR[6]
NAND_CLE
NAND_DATA[4]
CI_ADDR[9]
CI_ADDR[11]
CI_ADDR[12]
CI_ADDR[13]
CI_ADDR[8]
NAND_DATA[3]
NAND_DATA[5]
R165
R168
R171
R176
R178
R180
R182
R184
R188
R193
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
OPT
OPT
OPT
CI_ADDR[9],CI_ADDR[11],CI_ADDR[12],CI_ADDR[13]
TVM Crystal oscillator bias/gain control
0000: 210uA
0001: 390uA
0010: 570uA
0011: 730uA
0100: 890uA (O)
0111: 1290uA
1000: 1416uA
1111: 2196uA
0101, 0110, 1001, 1010, 1011, 1100, 1101, 1110: Reserved
CI_ADDR[8]:
0: RESETOUTb (in On/Off only) stay asserted until software releases them.
1: Fix amount of delay for de-assertion on RESETOUTb (in On/IOff only)
at end of RESETb pulse (O)
NAND_DATA[3]:
0: MIPS will boot from external flash (O)
1: MIPS will boot from ROM
NAND_DATA[5]:
0: FLASH MODE (O)
1: BSC_SLAVE(BBS) MODE
BCM_NVM_256K
IC103-*1
NVRAM
AT24C256C-SSHL-T
A0
VCC
1
8
A1
WP
2
7
A2
SCL
+3.3V_Normal
3
6
GND
SDA
4
5
BCM_NVM_1M
+3.3V_Normal
IC103
M24M01-HRMN6TP
NC
VCC
1
8
Write Protection
R169
0
E1
WP
- Low
: Normal Operation
2
7
A8'h
- High : Write Protection
E2
SCL
R190
33
3
6
SCL3_3.3V
VSS
SDA
R191
33
4
5
SDA3_3.3V
X101-*2
54MHz X-TAL
54MHz
X-TAL_1
1
4
GND_1
2
3
C113
CRYSTAL_BCM_KDS
12pF
R185
0
EAW58239604
54MHz_XTAL_N
DAISHINKU CORPORATION.
50V
3
2
X101-*1
X-TAL_2
GND_1
R189
54MHz
4
1
X-TAL_1
1M
GND_2
X-TAL_1
1
4
54MHz
OPT
GND_1
X101
R186
0
2
3
54MHz_XTAL_P
CRYSTAL_BCM_Sunny
C114
CRYSTAL_BCM_Lihom
12pF
EAW58812611
EAW60763703
50V
SUNNY ELECTRONICS CORPORATION
LIHOM CO., LTD.
BCM35230
2010.09.18
01
MAIN & NAND FLASH
LGE Internal Use Only
GND_2
X-TAL_2
GND_2
X-TAL_2
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