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Close to DDR Pin
+1.5V_FRC_DDR
+1.5V_FRC_DDR
R5301
1K
1%
MVREFCA
R5302
1K
1%
C5301
0.1uF
+1.5V_FRC_DDR
R5303
1K
1%
MVREFDQ
R5304
1K
1%
C5302
0.1uF
URSA5_DDR_NANYA_1600
URSA5_DDR_SS_1600
IC5301-*2
IC5301-*1
NT5CB64M16DP-DH
K4B1G1646G-BCK0
N3
M8
N3
M8
A0
VREFCA
A0
VREFCA
P7
P7
A1
A1
P3
P3
A2
A2
N2
H1
N2
H1
A3
VREFDQ
A3
VREFDQ
P8
P8
A4
A4
P2
P2
A5
A5
R8
L8
R8
L8
A6
ZQ
A6
ZQ
R2
R2
A7
A7
T8
T8
A8
A8
R3
B2
R3
B2
A9
VDD_1
A9
VDD_1
L7
D9
L7
D9
A10/AP
VDD_2
A10/AP
VDD_2
R7
G7
R7
G7
A11
VDD_3
A11
VDD_3
N7
K2
N7
K2
A12
VDD_4
A12/BC
VDD_4
T3
K8
T3
K8
NC_6
VDD_5
A13
VDD_5
N1
N1
VDD_6
VDD_6
M7
N9
M7
N9
NC_5
VDD_7
NC_5
VDD_7
R1
R1
VDD_8
VDD_8
M2
R9
M2
R9
BA0
VDD_9
BA0
VDD_9
N8
N8
BA1
BA1
M3
M3
BA2
BA2
A1
A1
VDDQ_1
VDDQ_1
J7
A8
J7
A8
CK
VDDQ_2
CK
VDDQ_2
K7
C1
K7
C1
CK
VDDQ_3
CK
VDDQ_3
K9
C9
K9
C9
CKE
VDDQ_4
CKE
VDDQ_4
D2
D2
VDDQ_5
VDDQ_5
L2
E9
L2
E9
CS
VDDQ_6
CS
VDDQ_6
K1
F1
K1
F1
ODT
VDDQ_7
ODT
VDDQ_7
J3
H2
J3
H2
RAS
VDDQ_8
RAS
VDDQ_8
K3
H9
K3
H9
CAS
VDDQ_9
CAS
VDDQ_9
L3
L3
WE
WE
J1
J1
NC_1
NC_1
T2
J9
T2
J9
RESET
NC_2
RESET
NC_2
L1
L1
NC_3
NC_3
L9
L9
NC_4
NC_4
F3
T7
F3
T7
DQSL
NC_7
DQSL
NC_6
G3
G3
DQSL
DQSL
C7
A9
C7
A9
DQSU
VSS_1
DQSU
VSS_1
B7
B3
B7
B3
DQSU
VSS_2
DQSU
VSS_2
E1
E1
VSS_3
VSS_3
E7
G8
E7
G8
DML
VSS_4
DML
VSS_4
D3
J2
D3
J2
DMU
VSS_5
DMU
VSS_5
J8
J8
VSS_6
VSS_6
E3
M1
E3
M1
DQL0
VSS_7
DQL0
VSS_7
F7
M9
F7
M9
DQL1
VSS_8
DQL1
VSS_8
F2
P1
F2
P1
DQL2
VSS_9
DQL2
VSS_9
F8
P9
F8
P9
DQL3
VSS_10
DQL3
VSS_10
H3
T1
H3
T1
DQL4
VSS_11
DQL4
VSS_11
H8
T9
H8
T9
DQL5
VSS_12
DQL5
VSS_12
G2
G2
DQL6
DQL6
H7
H7
DQL7
DQL7
B1
B1
VSSQ_1
VSSQ_1
D7
B9
D7
B9
DQU0
VSSQ_2
DQU0
VSSQ_2
C3
D1
C3
D1
DQU1
VSSQ_3
DQU1
VSSQ_3
C8
D8
C8
D8
DQU2
VSSQ_4
DQU2
VSSQ_4
C2
E2
C2
E2
DQU3
VSSQ_5
DQU3
VSSQ_5
A7
E8
A7
E8
DQU4
VSSQ_6
DQU4
VSSQ_6
A2
F9
A2
F9
DQU5
VSSQ_7
DQU5
VSSQ_7
B8
G1
B8
G1
DQU6
VSSQ_8
DQU6
VSSQ_8
A3
G9
A3
G9
DQU7
VSSQ_9
DQU7
VSSQ_9
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
+1.5V_FRC_DDR
DDR3 1.5V De-Cap
C5303
C5304
0.1uF
22uF
16V
10V
Place Close to DDR Pin
URSA5_DDR_HYNIX_1600
IC5301
H5TQ1G63DFR-PBC
M8
MVREFCA
VREFCA
A0
A1
A2
H1
MVREFDQ
VREFDQ
A3
A4
A5
R5305
L8
ZQ
A6
240
A7
1%
A8
B2
VDD_1
A9
D9
VDD_2
A10/AP
G7
VDD_3
A11
K2
VDD_4
A12/BC
K8
VDD_5
A13
N1
VDD_6
N9
VDD_7
A15
R1
VDD_8
R9
VDD_9
BA0
BA1
BA2
A1
VDDQ_1
A8
VDDQ_2
CK
C1
VDDQ_3
CK
C9
VDDQ_4
CKE
D2
VDDQ_5
+1.5V_FRC_DDR
E9
VDDQ_6
CS
F1
VDDQ_7
ODT
H2
VDDQ_8
RAS
H9
VDDQ_9
CAS
WE
J1
NC_1
J9
NC_2
RESET
L1
NC_3
L9
NC_4
T7
NC_6
DQSL
DQSL
A9
VSS_1
DQSU
B3
VSS_2
DQSU
E1
VSS_3
G8
VSS_4
DML
J2
VSS_5
DMU
J8
VSS_6
M1
VSS_7
DQL0
M9
VSS_8
DQL1
P1
VSS_9
DQL2
P9
VSS_10
DQL3
T1
VSS_11
DQL4
T9
VSS_12
DQL5
DQL6
DQL7
B1
VSSQ_1
B9
VSSQ_2
DQU0
D1
VSSQ_3
DQU1
D8
VSSQ_4
DQU2
E2
VSSQ_5
DQU3
E8
VSSQ_6
DQU4
F9
VSSQ_7
DQU5
G1
VSSQ_8
DQU6
G9
VSSQ_9
DQU7
Place near Memory
DDR3_A[0-13]
N3
DDR3_A[0]
P7
DDR3_A[1]
P3
DDR3_A[2]
N2
DDR3_A[3]
P8
DDR3_A[4]
DDR3_A[5]
P2
R8
DDR3_A[6]
R2
DDR3_A[7]
T8
DDR3_A[8]
R3
DDR3_A[9]
L7
DDR3_A[10]
R7
DDR3_A[11]
Place Close to DDR Pin
N7
DDR3_A[12]
T3
DDR3_A[13]
R5309
56
M7
R5310
M2
56
DDR3_BA0
C5315
N8
0.01uF
DDR3_BA1
M3
25V
DDR3_BA2
DDR3_MCK
J7
K7
K9
DDR3_MCKB
DDR3_CKE
L2
K1
DDR3_ODT
J3
DDR3_RASB
+1.5V_FRC_DDR
K3
DDR3_CASB
L3
DDR3_WEB
R5308
0
T2
DDR3_RESETB
F3
DDR3_DQSL
G3
DDR3_DQSLB
C7
DDR3_DQSU
B7
DDR3_DQSUB
E7
DDR3_DML
D3
DDR3_DQL[0-7]
DDR3_DMU
E3
DDR3_DQL[0]
DDR3_DQL[1]
F7
F2
DDR3_DQL[2]
F8
DDR3_DQL[3]
H3
DDR3_DQL[4]
H8
DDR3_DQL[5]
G2
DDR3_DQL[6]
H7
DDR3_DQL[7]
D7
DDR3_DQU[0]
C3
DDR3_DQU[1]
C8
DDR3_DQU[2]
C2
DDR3_DQU[3]
A7
DDR3_DQU[4]
A2
DDR3_DQU[5]
B8
DDR3_DQU[6]
A3
DDR3_DQU[7]
DDR3_DQU[0-7]
Place the serail damping resistors
in the middle of DRAM pattern
R5311
22
FRC_DMU
DDR3_DMU
R5312
22
FRC_DQSL
DDR3_DQSL
R5313
22
FRC_DQSLB
DDR3_DQSLB
R5314
22
FRC_DQSU
DDR3_DQSU
R5315
22
FRC_DQSUB
DDR3_DQSUB
R5316
22
FRC_DML
DDR3_DML
R5317
22
FRC_ODT
DDR3_ODT
R5318
22
FRC_RASB
DDR3_RASB
R5319
22
FRC_CKE
DDR3_CKE
DDR3_MCK
R5320
22
FRC_MCLK
DDR3_MCK
DDR3_MCKB
R5321
22
FRC_MCLKB
DDR3_MCKB
R5322
22
FRC_DDR3_RESETB
DDR3_RESETB
AR5301
FRC_A[10]
DDR3_A[10]
FRC_BA1
DDR3_BA1
FRC_A[12]
DDR3_A[12]
FRC_A[4]
DDR3_A[4]
22
AR5302
FRC_A[6]
DDR3_A[6]
FRC_A[8]
DDR3_A[8]
FRC_A[1]
DDR3_A[1]
FRC_A[11]
DDR3_A[11]
22
AR5303
FRC_A[0]
DDR3_A[0]
FRC_A[2]
DDR3_A[2]
FRC_A[13]
DDR3_A[13]
FRC_A[9]
DDR3_A[9]
22
AR5304
FRC_A[7]
DDR3_A[7]
FRC_A[5]
DDR3_A[5]
FRC_A[3]
DDR3_A[3]
22
AR5305
FRC_BA2
DDR3_BA2
FRC_BA0
DDR3_BA0
FRC_WEB
DDR3_WEB
FRC_CASB
DDR3_CASB
22
MStar URSA5
DDR3 4Mbit
AR5306
FRC_DQL[4]
DDR3_DQL[4]
FRC_DQL[6]
DDR3_DQL[6]
FRC_DQL[2]
DDR3_DQL[2]
FRC_DQL[0]
DDR3_DQL[0]
22
AR5307
FRC_DQU[5]
DDR3_DQU[5]
FRC_DQU[3]
DDR3_DQU[3]
FRC_DQU[7]
DDR3_DQU[7]
FRC_DQU[1]
DDR3_DQU[1]
22
AR5308
FRC_DQU[4]
DDR3_DQU[4]
FRC_DQU[6]
DDR3_DQU[6]
FRC_DQU[2]
DDR3_DQU[2]
FRC_DQU[0]
DDR3_DQU[0]
22
AR5309
FRC_DQL[3]
DDR3_DQL[3]
FRC_DQL[1]
DDR3_DQL[1]
FRC_DQL[5]
DDR3_DQL[5]
FRC_DQL[7]
DDR3_DQL[7]
22
2010. 08.18
53
LGE Internal Use Only
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