Kenwood TS-711A Instruction Manual page 27

(2SC2668) and then converting to 12.8 - 16.8 MHz.
Then, the resultant signal is amplified in O30 (TA7302)
and divided at a frequency division coefficient of from
6400 - 8400 so that a 2 kHz output is obtained. Further,
10.24 MHz is also devided by 1/10 at Q36 and again de-
vided by 1/5, and the resultant signal is phase compared
with the 2 kHz reference signal at Q21 (MC145155P).
The PD (Phase Detector) output is converted to a DC loop
correction voltage by a 3 transistor stage LPF (Q25 — 27:
2SC2459) to control the VCO (Q28).
Additionally, part of the 64 - 68 MHz VCO output which
passed through buffer amplifier Q29 is subject to 1/200
division by divider IC 023: M54459L for 1/100 division
and Q22: SN74LS9ON for 1/2 division through buffer
Q24 (2SC260 (Y, O)). The output of O22, therefore, be-
comes 320 - 340 kHz at a 10 kHz step rate. This output
and the output of the carrier OSC are input to mixer Q6
(SN16913P). A 11.025 MHz output is taken through a
ceramic filter and a buffer (Q5: 2SC2668). Then, this
11.025 MHz output is mixed at Q4 (SN16913P) with a
20.48 MHz signal which is obtained by multiplying 10.24
MHz by two at Q40 (2SC2668) so that an output of
31.505 MHz is obtained.
Then, this 31.505 MHz output is input to mixer Q3
(SN16913P) as the loop A local OSC signal.
Loop A is a dual modulus type PLL with a 20 kHz compari-
son frequency. Prescaler 020 (wPB555) operates at either
a 1/16 or 1/17 division ratio. The VCO output (113.735 -
117.735 MHz) (Q10: 2SK192A) in loop A is separated
into the HET (Heterodyne) output and the input to mixer
Q3 (SN16913P) through buffer Q11 (2SC2668). Mixer
Q3 output (80 - 90 MHz) is amplified in a 2 transistor
stage amplifier (Q17, 18: 2SC2668) through a 80 - 95
MHz BPF and is input to prescaler Q20.
The prescaler, connected with PLL IC Q19, forms a swal-
low counter to divide this input at a frequency division
coefficient NA = 4112 to 4312. This signal is phase-
compared with the 20 kHz reference signal obtained by
dividing 10.24 MHz by two and 1/256 division of 5.12
MHz. The output is DC converted by a 3 transistor LPF
stage (Q12, 13, 14) to control the VCO (Q10). HET output
is obtained by amplifying the VCO output (Q10) by transis-
tor Q1 (2SC2668).
Comparison frequency derivation:
[Loop A:]
The 10.24 MHz TCXO output is amplified by two transis-
tor stages (034, 35: 2SC2458) via buffers (033, 38:
2SC2458), is devided by 1/2 (Q36/2) 5.12 MHz, which in
turn is input to PLL IC Q19. This input is divided 1/256 by
the divider inside Q19 20 kHz, which is the comparison
frequency.
[Loop B:]
The 5.12 MHz output in loop A is further divided 1/5 by
divider Q36/2 to 1.024 MHz. This signal is then input to
PLL IC Q21 and is divided 1/512 by the divider contained
inside Q21 to 2 kHz, which is the comparison signal.
For unlock detection, the output of PLL IC Q19 pin 9 in
loop A is used. The poweer supply to buffer Q1 is
switched by transistors 015 and O16.
The carrier X'tal OSC is switched by diode switches D4
and D5. The bias voltage for D4 is applied from the 8C
(8V DC common
supply) line, and is independent of the
mode. However, in the LSB mode, D4 and D5 can be se-
lected by the ratios of R37/R38 and R40/R39.
1) Basic configuration
The microprocessor, which has an 8-bit (ROM, 6-Kbyte)
main CPU (IC24: uPD78026-087-36) and a 4-bit
(ROM, 2-Kbyte) sub CPU (IC20: uPD7507G-575-00),
uses a CMOS RAM (IC14: MB8418-20LP-GRA) with a
capacity of 8 bits x 2K bytes as the external memory IC,
the I/O interface IC (IC16: "PD8255AC-5) for I/O port
extension and three 6-bit D-flip-flop ICs (IC12, 17, 22:
74LS174). In addition, it is provided with a 24-pin IC
socket for the external ROM for optional personal com-
puter interface.
These ICs, connected in parallel with the data bus in the
main CPU, exchange data with the main CPU synchron-
ized by timing signals WR or RD of the main CPU, or CS
signal from IC15. 1C15, a 3 to 8 bit line decoder, de-
codes inputs to address lines PE13 - 15 in the main
CPU to generate the chip select signal (CS). In addition,
1C13 takes an OR logic between signals CS and WR to
supply the clock pulse to IC12, IC17 and IC22, all of
which are used as latches.
The main CPU
controls the frequency, mode, offset,
tone, display, memory, dial click mechanism, DCS sys-
tem, voice synthesis, etc. and accepts interface with
the sub CPU or an external personal computers.
The sub CPU interrfaces with the main CPU or the MO-
DEM IC, IC19, to handles digital signal code conversion
and control tone ON/OFF and other such operation.
2
DCS system control section
27