Pioneer CLD-D503 Service Manual page 9

CLD-D503, CLD-D57(
Mi PDO146A (MAIN ASSY IC500)
®@ Digital video processor
@ Pin Function
1 Power pin for reference system
Connected to +5V.
XSGCSY Reference composite synchronization output
2
Reference composite synchronization is output at negative logic.
Delay can be controlled by serial command.
3 | WFM MMEMSYS:1! Field monitor output for write system
Outputs "H" when in odd field.
XCHA MEMSYS:0 } Character input pin for write system
Inputs "L" during character insertion.
SYS:1 | TBC H synchronization output
Outputs time base-corrected H synchronization at negative logic.
MEM
= SSG phase detection signal output
Outputs "H" when phase difference of H, V synchronization between Playback system
(after TBC) and SSG system is small enough.
MEMSYS:1 | TBC V synchronization output
Outputs time base-corrected V synchronization at negative logic.
MEMSYS:0_ | Clock output for character generation
Outputs 2Fsc.
FCH - MEMSYS:1 | Field change input .
Switches field of SSG when "H".
MEMSYS:0 | Character frame input pin
Inputs "L" when character frame is inserted.
CK Reference inverted CLK output
Reference CLK is reversed and output.
Reference CLK output
: Data output 2
fis [DOO | Data ouput
17 | DCOREF | D/Aconverter reference for DCO ~
Normally connected to DAGND via 0.1 WF of laminated ceramic capacitor.
18 | INSSY Synchronization output for insertion
Synchronization insert pin.
OPEN DRAIN output.
DAREF D/A converter reference for video
Normally connected to DAGND via 0.1 uF of laminated ceramic capacitor.
20 | VOUT TBC (time base-corrected) video output pin
Synchronization must be inserted by pin 18 (INSSY).
Note) Pin functions of pins 3- 6 differ depending on the mode (MEMSYS) of interface.
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Outputs TBC (time base-corrected) video signal to support memory. Serial interface
performs this setting. D07 is MSB, DOO is LSB.
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