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CLD-D503, CLD-D570
i _C78681E (MAIN ASSY IC802)
@ Servo-control
& EFM demodulation
@ Outline of Functions
1) If HF signal is input, slices HF signal at accurate level, and
converts it to EFM signal. After this compares the phase
with VCO, and regenerates an average 4.3218 MHz PLL
clock.
2) Controls rotation of spindle motor by the frame phase
difference signal generated from the playback clock and
reference clock.
3) Demodulates and converts EFM signal to 8-bit symbol
data.
@ Block Diagram
a
q
9
v
5
3
5
2
6
&
{6
14-82-18 -
|
H
:
Slice level
VCO clock
Sein
control
oscillation
i
clock control
|
|
a
Synchronization
FSEQ [19
detection EFM
demodulation
ie
CLV + {10}
CLV
civ—[l]
digital servo
V/P 112)
I
PW.SBCK |46)
Sub-code sepa-
ration
Q CRC
SBSY.SFSY [47
|
cc
wRQ.SQOuT 50—f
com
C1, C2 error detection
correction flag process
4) Separates subcode from EFM demodulation signal, and
outputs to external microprocessor.
5) Buffers EFM demodulation signal at internal ROM, and
performs jitter-absorption by disc rotation fluctuation of
+4 frames.
6) Performs unscramble and deinterleaving to rearrange EFM
demodulation signals in a specified order.
7) Detects and corrects error signals, and performs a flag
process (C1, double; C2, double correction system).
ammamm
is
Saaeaa
8 8
1} (91 23) 28 61) G2--24}--[5}—--—---—--
—--—-------}
|
=
2Kx8bit
RAM address
H
RAM
generator
|
|
i
| —__
41] ceFcLk
=]
Interpolation
38] LRSY
mute (bilingual)
(42| car
[40] RoMouT
!
|
|
1
CQCK {54}
COIN 153)
Servo-
: fede I
commander
DEMO/27
Digital
OUT
DOUT
DAC OUT
interface
XTAL system
timing generator
!
|
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