Table of Contents
Advertisement
CLD-D503, CLD-D570
@ PAO0O23AD (MAIN ASSY 1IC401)
@ FM Detector
@ Pin Function
[Pinname |
Function
Ne| Pinname | ___—'Function ———SSS—*d
Zz QO w
vec__|
+5V powerpin
BIAS
BIAS pin
° c 5
;
REG
Constant voltage pin
RF input pin (positive)
Z
+
VEE
-5V power pin
Delay time setting pin
[Nes
Nc
mba
mm fe ~
Wir
o
6
b
NC2
14| Nes
i PAO058A (MAIN ASSY IC400)
® Video demodulator
@ Pinname
Pin name
Power pin
<
Ar
218
to
2
Drop-out pulse output pin
Noise reduction 2 input pin
Outputs drop-out pulse if drop out is detected.
NRR2
Adjusts noise reduction level using value
H level (during drop-out) > 4.3V
Sf cicbaianmnceried bianca
iaand
L level (when normal) > 0.2V
B NRR1
OND.
Soa
a
Eee
Composite sink pulse output pin
-
H level
Vcc
Input pin
L level 0.2V
GND2
DATA
Phillips code pulse output pin
21|
DEEM
De-emphasis amplifier output pin
H level — 4.3V
ee
3
3
Appropriate feedback circuit is inserted
L level — 0.2V
between this pin and de-emphasis amplifier
CSIN
Input pin for synchronization separation
input pin.
Diode clamp input
Output level > 1.1 V p-p
Clamp level > about 1.9V
22!
DEEMIN
De-emphasis amplifier input pin
Input level + 200 mV p-p
PEDIN
Input pin for synchronization separation
Hard-clamped at pedestal level
23|
RDOS
Clamp level — about 2.7V
GND1
LPF output
pin for synchronization separation
ame
GND3
Output level — 1V p-p (GAIN 0dB)
:
F
:
25}
CINH
OTTOM = | Low side reference voltage pin for A/D
conversions
10 | RE20K
Resistance pin for internal constant current
supply. Connected to 20K 2 resistance.
26|
DINH
TOP
;
12 | VOUT
DOS frequency sensitivity adjustment pin
Adjusts frequency sensitivity of DOS using
resistance inserted between this pin and GND.
Recommended resistance
> 20 KQ.
{ay fas]
*T
Clamp inhibit pin
Controls clamp operation of 5, 6, 13 pins
OV > clamp
5V — clamp inhibit
Phillips code pulse output control pin
OV — output inhibit
5V > output
HIGH side reference voltage pin for A/D
conversion
Outputs video signal that is clamped by
synchronization chip for A/D conversion.
Output level + 2V p-p (GAIN 6dB)
Synchronization signal level — about 1.67V
27}
NRINI
Noise reduction 1
Control pin
;
0V + ON
5V — OFF
Synchronization signal clamp input pin
Input level
+ 1V p-p
13 | SCLPIN
28]
DOSIN
DOS input pin
' | Input level — 500 mV p-p
14 | NROUT
Noise reduction circuit output pin
30]
NC2
;
Ouiput level) LV pp
a
Advertisement
Table of Contents
