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Circuit Diagrams and PWB Layouts
SSB: Interface STI7100
1
2
INTERFACE STI7100
B11D
A
B
C
IAC4
2AC0
1u0
3AC1
560R
IAC5
D
PCMOUT2
PCMOUT3
PCMOUT4
E
3139 283 3003.1
1
2
PB52.1HU LB
7.
3
4
7A00-1
STI7100YWC
Φ
AV
INTERFACE
L34
D34
0
R0OUT
L33
F34
1
VIDANA
G0OUT
K34
E34
2
B0OUT
K33
3
J34
D33
4
IDUMPR0
J33
F33
5
VIDANA
IDUMPG0
H34
E33
6
IDUMPB0
H33
7
U30
A34
8
VIDDIGOUTYC
C1OUT
T31
C34
9
VIDANA
CV1OUT
T30
B34
10
Y1OUT
R31
11
R30
A33
12
IDUMPC1
P31
C33
13
IDUMPCV1
VIDANA
P30
B33
14
IDUMPY1
N31
15
A31
REXT0
M34
VIDANA
A32
VSYNC
REXT1
M33
VIDDIGOUT
HSYNC
B31
GNDAREXT0
C28
VIDANA
B32
VBGFIL
GNDAREXT1
C27
AUDANA
IREF
B28
U33
MRIGHT
TXCP
A28
U34
PRIGHT
TXCN
T33
AUDANAOUT
TX0P
B27
T34
MLEFT
TX0N
A27
R33
PLEFT
TMDS
TX1P
R34
TX1N
D24
P33
SPDIF
TX2P
E24
P34
SCLK
TX2N
E26
AUDOUT
LRCLK
FAC0
D26
T32
PCMCLK
TMDSREF
A25
0
COMPENSATION RESISTOR
B25
D29
1
DATAIN
C25
D28
2
AUDPCMOUT
AUDDIG
DSTRBIN
D25
E28
3
DLRCLKIN
E25
4
3
4
77
5
6
+3V3
2AC1
+3V3
1u0
2AC2
100n
IAC2
3AC2
12K
3AC3
22K
3AC4
12K
3AC5
IAC3
22K
DRXC+
DRXC-
DRX0+
DRX0-
DRX1+
DRX1-
DRX2+
DRX2-
3AC9
+3V3TMDS
100R
3ACC
100R
5
6
7
8
B11D
+3V3
7AC0
BC847BW
2AC3
3AC8
IAC1
68R
100n
I_17501_082.eps
7
8
2AC0 D2
2AC1 B6
2AC2 C6
2AC3 C7
3AC1 D1
3AC2 C4
3AC3 C4
3AC4 C4
3AC5 D4
3AC6 B6
3AC7 C6
A
3AC8 C7
3AC9 D4
3ACA C6
3ACB C6
3ACC E4
7A00-1 B3
7AC0 B6
FAC0 D4
IAC1 C7
IAC2 C4
IAC3 D4
IAC4 D2
B
IAC5 D2
C
D
E
280708
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