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No
No
Code = 5
Switch AVC PNX85xx
in reset (active low)
Wait 10ms
Switch the NVM reset
line HIGH.
Disable all supply related protections and
switch off the +2V5, +3V3 DC/DC converter.
Wait 5ms
switch off the remaining DC/DC
converters
Switch POD-MODE and ON-MODE
3-th try?
I/O line high.
Service Modes, Error Codes, and Fault Finding
Switch LOW the RESET-NVM_WP-NANDFLASH line. Add a 2ms delay before
trying to address the NVM to allow correct NVM initialization.
No
Release AVC system reset
Feed warm boot script
Boot process of the PNX5050 also starts at this point.
No
No
Code = 53
No
Reset the Pacific by pulling LOW the Pacific
Figure 5-4 "Off" to "Semi Stand-by" flowchart (part 2)
SUPPLY-FAULT I/O line
No
is High?
Yes
Enable the supply fault detection
algorithm
Set I²C slave address
of Standby µP to (A0h)
Detect EJTAG debug probe
(pulling pin of the probe interface to
ground by inserting EJTAG probe)
EJTAG probe
connected ?
No
Cold boot?
Yes
Release AVC system reset
Feed cold boot script
Bootscript ready
in 1250 ms?
Yes
Set I²C slave address
of Standby µP to (60h)
RPC start (comm. protocol)
Flash to Ram image
transfer succeeded
within 30s?
Yes
SW initialization
succeeded
within 20s?
Yes
Enable Alive check mechanism
MIPS reads the wake up reason
from standby µP.
In case of an LCD set, check the
Power-OK display line
Power-ok display high ?
Yes
hardware reset line during 100ms.
PB52.1HU LB
Supply fault error
SP
This will allow access to NVM and
NAND FLASH and can not be done
earlier because the FLASH needs to
be in Write Protect as long as the
supplies are not available.
An EJTAG probe (e.g. WindPower ICE probe) can
be connected for Linux Kernel debugging purposes.
Yes
Release AVC system reset
Feed initializing boot script
disable alive mechanism
Wait until AVC starts to
communicate
Log power-ok error and enter
No
protection
MP
No
5.
EN 19
The supply fault line is an OR
function of DCDC, DCDC5050
and POD/CI supply switch.
H_17650_094b.eps
090826
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