Memory Mapping - Sharp OZ-9600II Service Manual

OZ-9600 II
1Q~-9200
@ Read mode Pe LE es
When CE and OE are low, it goes into the read mode. The output
data will be sent onto the data bus through the data i/o lines
(VO0~I/O7) with an address data output delay time (tACC) after
the address has been set, or with an data output delay time (tOE)
from a high to low transition of OE.
@ Standby mode .
When CE is'set to a high state, it goes into the standby mode. In
this mode, /O0~1/O7 turn high impedance regardless of what
state OE is. ;
@® Write mode
(a) Byte write mode a t e
When CE and WE are set low and OE high, it goes into the
write mode. it is possible for the pPD28C64GxX to control CE
and WE. Address is latched at a high to low transition of CE
or WE whichever appeared later. The data is latched a a high
to low transition appeared earlier. The. automatic
erasure/write completes within 12ms of the write cycle time
(tWC). ;
(b) Page write mode
The wPD28C64GX allows page write up to 32 bytes per
page. Utilizing this feature, all bytes will be completed to
write within 3 seconds. The »PD28C64GX comprises 246
pages x 32 bytes. To use the page write function, the page is
assigned through the address A5~A12, then the data are
sequentially written through the address AO~A4 or may be
written at random. However, unless a next address is sent
within 100s of the byte load cycle, it starts the internal auto-
matic erasure or write operation. No page can be changed in
a course of the write cycle. :
@® Chip erase mode
The pPD28C64GxX goes into the chip erase mode when OE=VIHH
(15V0.5VO and CE=WEs="L". In this occasion, data inputs
/00~1/07 must be set to high level. Address input is "don't care".
© Write inhibit mode
When OE is set low or WE is set high, it goes into the write inhibit
mode and disables to write anything. ;
-16-
3. Memory mapping
Main memory | CARD
~ ~ 99000h 8000h
e e Sra oe aT | eR etc ATC
iat cpuvo) | beer 8100h
System VO pe
20000) | eee eee hee , 3400h |_—~Pohibited area__|
Prohibited area
CARD RAM1
AM2N)
pe ene 5 an
: Touch panel
8900h =
secant
60000h Prohibited area
'Touch panel
(CERAM2) Prohibited area
80000h
CEIN
CE8N
A0000h
({CERAM1) ;
coooon Seep ieenugeteenpteias
cee ceree
Ppoee ete ae oe ot
reer CESIN 'E3*CEBON™ E3*CESON -
MEIN GARD ACTIVE
CEO 80000~BFFFF L
CE1 80000~BFFFF L
CE2 20000~3FFFF H
CE3 NC -
CE4 8000~8FFF H
CE5 H
CE6 COOOO~FFFFF L
CE7 40000~7FFFF° L
4. LCD booster circuit
vec