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DDR5 Only DIMM Configuration
SPR IMC#
Channel
DDR5
1+0
2+0
4+0
6+0
8+0
12+0
16+0
⚠
Note
1. There should be at least one DDR5 DIMM per socket.
2. Interleaving way limitations: 3-way Channel and 3-Way Rank interleaving are not
supported. A 2-Way + A 1-Way would be implemented instead of A 3-Way for those
channel DIMM configurations. A 2-way interleave method is implemented across 3
ranks in a channel.
3. Sapphire Rapids processor erratum prevents using 6-way Hemisphere mode,
6-way All-to-All mode would be the default for 6 channel configurations.
4. If the system detects a DIMM fails at boot time, BIOS takes map-out actions for a
fallback to the nearest reduced POR config in the table.
5. Rank sparing, ADDDC, channel mirroring, and Hemisphere/ quad modes are not
supported with SGX.
6. SPR+HBM does not support Hemisphere/ SNC2 modes.
7. UMA default - see 6-DIMM configurations, x6 interleaving for All-to-All mode.
38
Memory
IMC3
H
G
F
Chan 7
Chan 6
Chan 5
H1 H2 G1 G2 F1 F2 E1 E2
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
"V" indicates DIMMs are populated with DDR5.
IMC2
E
A
Chan 4
Chan 0
A2 A1 B2 B1 C2 C1 D2 D1
V
C
P
V
U
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IMC0
IMC1
B
C
Chan 1
Chan 2
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
D
Chan 3
V
V
V
V
V
V
V
V
V
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