Pci Interrupt Pins; Address/Data Pins - HighPoint HPT366 Data Manual

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PCI Interrupt Pins

Pin Number Pin Name Type
133 INTA_
134 INTB_

Address/Data Pins

Pin Number Pin Name Type
140,141,142, AD(31-0)
143,2,3,4,5,
8,9,10,11,12,
14,15,16,29,
30,31,32,33,
34,36,37,39,
41,42,43,44,
45,47,48
6,20,28,38 C_BE_(3-0) I/O
27 PAR
Description
O Interrupt A is used to request an interrupt.
O Interrupt B is used to request an interrupt and only has meaning
on a multi-function device.
Description
I/O Physical longword Address and Data are multiplexed on the
same PCI pins. During the first clock of a transaction, AD(31-0)
contain a physical byte address. During subsequent clocks,
AD(31-0) contain data. A bus transaction consists of an address
phase followed by one or more data phase. PCI supports both
read and write bursts. AD(7-0) define the least significant byte,
and AD(31-24) define the most significant byte.
Bus command and byte enables are multiplexed on the same
PCI pins. During the address phase of a transaction, C_BE_(3-0)
define the bus command. During the data phase, C_BE_(3-0)
are used as byte enables. The byte enables determine which
byte lanes carry meaningful data. C_BE_0 applies to byte 0,
and C_BE_3 to byte 3.
I/O Parity is the even parity bit that protects the AD(31-0) and
C_BE_(3-0) lines. During address phase, both the address and
command bits are covered. During data phase, both data and
byte enables are covered.
2-5
Signal Descriptions/144 Pins Listing
HPT366 Data Manual
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