ASROCK AMD A620 Series Setup Manual page 36

TrdrdScL
The minimum number of cycles from the last clock of virtual CAS of the first read-
burst operation to the clock in which CAS is asserted for a following read-burst
operation in the same chipselect in the same bank group.
TrdrdSc
The minimum number of cycles from the last clock of virtual CAS of the first read-
burst operation to the clock in which CAS is asserted for a following read-burst
operation in the same chipselect.
TrdrdSd
The minimum number of cycles from the last clock of virtual CAS of the first read-
burst operation to the clock in which CAS is asserted for a following read-burst
operation in the same DIMM.
TrdrdDd
The minimum number of cycles from the last clock of virtual CAS of the first read-
burst operation to the clock in which CAS is asserted for a following read-burst
operation in a different DIMM.
TwrwrScL
The minimum number of cycles from the last clock of virtual CAS of a first write-
burst operation to the clock in which CAS is asserted for a following write-burst
operation in the same bank group.
TwrwrSc
The minimum number of cycles from the last clock of virtual CAS of the first write-
burst operation to the clock in which CAS is asserted for a following write-burst
operation in the same chipselect.
TwrwrSd
The minimum number of cycles from the last clock of virtual CAS of the first write-
burst operation to the clock in which CAS is asserted for a following write-burst
operation in the same DIMM.
TwrwrDd
The minimum number of cycles from the last clock of virtual CAS of the first write-
burst operation to the clock in which CAS is asserted for a following write-burst
operation in a different DIMM.
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