LG BD390 Service Manual page 94

5. BCM7601-1 CIRCUIT DIAGRAM
VCC_1V2 SATA_PLLVDD12
L513
HB2012_1000
C538
C537
22uF
0.1uF
DGND
Must be placed near BCM7601
VCC_1V2 PLL_AVDD12
D2 CLK27_XTALN
L512 D2 CLK27_XTALP
4.7UH
Place under the
C532 C510
BCM7601 near ball
22uF
0.1uF
2:F3 CLK33_OUT_PCI_CLK_IN
DGND
VCC_3V3 VDAC_VDD33
L501 0.1uF C533
VDAC_VDD33
0.01uF C534
HB2012_1000
C520
C529 0.1uF
C535
22uF
0.1uF
0.01uF
C536
4:F3 BSC_S_SCL
4:F3
BSC_S_SDA
DGND
6:F5 VDAC_Pb
6:F5 VDAC_Y
6:F5 VDAC_Pr
6:D4 VDAC_CVBS
R501 562(1%)
DGND
Close to 7601
6:I6 HDMI_SCL
6:I6
HDMI_SDA
6:I7 HDMI_0_P
6:I6 HDMI_0_N
6:I7 HDMI_1_P
6:I7 HDMI_1_N
6:I7 HDMI_2_P
VCC_1V2 USB_VDD12 6:I7 HDMI_2_N
DGND
6:I6 HDMI_CLK_P
6:I6 HDMI_CLK_N
L506
HB2012_1000
C523
C541
OPEN_22uF
0.1uF
DGND
6:I6 HDMI_HTPLG
DGND
4:D7 I2S_CLK
4:D7 I2S_LRCLK
4:D7 I2S_DATA0
VCC_1V2 EPHY_VDD12
4:D7 I2S_DATA1
4:D7;H6 I2S_DATA2
L514 4:D7;H6
I2S_DATA3
HB2012_1000
C540
0.1uF
DGND
VCC_1V2 HDMI_PVDD12
L515
HB2012_1000 C543
C544
OPEN_22uF
0.1uF
DGND
Close to 7601 and avoid heat sink
C3 CLK27_XTALN
C3 CLK27_XTALP
R518 R511
18 18
X504
27MHz/18pFCL
C504 C518
30pF 30pF
DGND
BCM7601 BGA 507Pin (21 x 21) Broadcom
IC201
B13 CLK27_XTALN
C13 CLK27_XTALP
SGPIO_03
E13
ALT27_XTALN
SGPIO_02
E12
ALT27_XTALP
GPIO_19
H19 AA24
DGND ALT_XTAL_SEL
GPIO_14
G13 AB23
PLL_AVDD12 PLL_AVDD12 GPIO_13
F13
PLL_AVSS GPIO_12
R5C8 33
G15 CLK33_OUT AA21
GPIO_11
AB24
D13 PLL_TESTOUT
GPIO_10
D16
BYP_SYS800_PLL
GPIO_09
A14
BYP_CPU_CLK
GPIO_07
C15 AB25
BYP_216_CLK
GPIO_06
C16
BYP_SYS9_CLK BSC_M_SDA0
E15
BYP_AVD_CLK BSC_M_SCL0
B14 BYP_DSP_CLK
UART_TX2_GPIO_15
DGND E16 TEST_MODE0
UART_RX2_GPIO_16
F16 AB21
TEST_MODE1
UART_TX2_GPIO_05
B16 AA23
TEST_MODE2
UART_RX2_GPIO_04
A16 AA22
TEST_MODE3
UART_TX1
G14
TP594 EJTAG_nTRST UART_RX1
A13
TP518 EJTAG_TMS UART_TX0
D14 EJTAG_TCK
TP519 UART_RX0
E14 EJTAG_TDI
TP520 nRESET_OUT
F15
EJTAG_TDO
TP521 nFP_4SEC_RESET
C14
EJTAG_CE
TP522 nRESET
D22
BSC_S_SCL
IR_OUT
C22
BSC_S_SDA IR_IN0
F10
VDAC0_REG EPHY_TDP
E10 VDAC1_REG
EPHY_TDN
C12 VDAC0_0
EPHY_RDP
B12
VDAC0_1
EPHY_RDN
D12
VDAC0_2
EPHY_RDAC
E11
VDAC1_0
EPHY_ATEST
F11
VDAC1_1 EPHY_AGND
D11
VDAC1_2 EPHY_AVDD12
D10 VDAC_RBIAS
SATA_AVSS
DGND G10 VDAC_AVSS
SATA_PLLVDD12
A12
VDAC_AVSS
SATA_PLLTESTN
G11
VDAC_VDD33 VDAC_AVDD33
SATA_PLLTESTP
E7
HDMI_SCL
SATA_TXDN
F7
HDMI_SDA SATA_TXDP
A9
HDMI_0_P SATA_RXDN
B9 HDMI_0_N
SATA_RXDP
D8 HDMI_1_P
USB_RREF
D9
HDMI_1_N
USB1_PWRFLT
A8
HDMI_2_P
USB1_PWRON
B8
HDMI_2_N
USB1_DN
C9
HDMI_CLK_P USB1_DP
C10
HDMI_CLK_N USB0_PWRFLT
G9 HDMI_PDVDD12
HDMI_PVDD12 USB0_PWRON
F8 HDMI_PLLCAP
USB0_DN
R553 12K(1%) D7
DGND HDMI_EXT12K
USB0_DP
A10
DGND HDMI_GND
USB_MONCDR
R554 27K E8
HDMI_CEC_RES
USB_MONPLL
R588 0 C8
HDMI_CEC USB_AVSS
C7
HDMI_HTPLG USB_PLLVDD12
R560 33 Y21 I2S_CLOCK AC22
I2S_S_DATA
33
R561 U23 I2S_LR
I2S_S_LR
R562 33 U21
I2S_DATA0
I2S_S_CLK
R563 33 U20
I2S_DATA1
AUD0_SPDIF
R564 33 U22
I2S_DATA2
AUD_FS_CLK0
R565 33 AA25
I2S_DATA3
R508
OPEN_4.7k
4:J5;F4 nRESET
OPEN
F3 nSELF_RST/GPIO_14
R571
Value
VCC_3V3
4:F5;F3 SGPIO01/BSC_M0_SDA
4:F5;F4 SGPIO00/BSC_M0_SCL
F3
EJECT_BTN/SGPIO_03
F3;F4 STANDBY_BTN/SGPIO_02
TP5B3
F3 STANDBY/GPIO_07
T20
EJECT_BTN/SGPIO_03 G3
V24
STANDBY_BTN/SGPIO_02 F4;G3
Y25 TP5A8
GPIO_19_UART_PROTECTION 4:H8
nSELF_RST/GPIO_14 E7
7:B5
PSU_ON/GPIO_13
V19
RESET_AUDIO_CARD/GPIO_12 4:E8
TP5B1
TP5B0
Y23 TP5A9
W23
G3
STANDBY/GPIO_07
6:B5
AUD_MUTE/GPIO_06
T22
4:F5;G2
SGPIO01/BSC_M0_SDA
T19
SGPIO00/BSC_M0_SCL 4:F5;G3
U19
UART_TX3 4:F6
V22
UART_RX3
4:F6
UART_TX2 4:I8;H6
UART_RX2 4:I8
UART_TX1
4:G8;H6
V21
UART_RX1 4:G8
W22
UART_TX0 4:H7;H6
V23 UART_RX0
4:H7
G19 TP523
G20 OPEN R570
STANDBY_BTN/SGPIO_02 F3;G3
B22 1k R5F4
nRESET 4:J5;E7
A20
B23
G4
EPHY_TDP 4:J6
F4
EPHY_TDN 4:J6
G6
EPHY_RDP 4:J6
G5
4:J7
EPHY_RDN
F3
DGND
K7 1.24K(1%) R567
F1
DGND
J7
EPHY_VDD12
A4
DGND
H7
SATA_PLLVDD12
C6
C5
A6
SATA_TXDN1 4:I2
B6
SATA_TXDP1 4:I2
A5
SATA_RXDN1 4:I2 100pF C539
B5
SATA_RXDP1 4:I2
C3 3.9K(1%) R566
DGND
B3
USB1_PWRFLT 4:B4
D4
USB1_PWRON 4:B4
D2
4:B4
USB1_DN
D3
4:B5
USB1_DP
C4
USB0_PWRFLT 4:B4
B2
USB0_PWRON 4:B4;H6
E3
USB0_DN 4:B5
E4
USB0_DP 4:B5
C2
B4
D1
DGND
F5
USB_VDD12
R559 33 H6;6:B6
I2S_S_DATA
V25 33
R558 6:B6
I2S_S_LR
Y22 R557 33
6:B6
I2S_S_CLK
U25 R556 33
H6;6:J2
AUD0_SPDIF
V20 R555 33
4:B7;6:B5
AUD_FS_CLK0
2:F3
2:G3 EBI_ADDR[24]
2:G3 EBI_ADDR[25]
4:D7;C5 I2S_DATA2
4:D7;C5 I2S_DATA3
2:F2;4:B2
2:F2;4:B2
4:B4;F5 USB0_PWRON
2:F3;4:B2
F5;6:B6
I2S_S_DATA
2:F3
2:F3 PCI_nGNT0
VCC_3V3
2:F2;4:B2
F5;6:J2 AUD0_SPDIF
4:I8;F4
4:G8;F4
4:H7;F4
C515 CA501
0.1uF 22uF/16V
IC502
MCP1319-29
DGND
VCC_3V3
1 5 TP517
RST VDD
2
VSS
OPEN_1k R509
3 4
RST MR
C522
OPEN_0.1uF
DGND
DGND
3-85 3-86
BCM7601 STRAP OPTIONS
F e i d l a N e m Signal bit D s e r c p i i t n o
0:All straps must be set on board
1 Strap_use_defaults EBI_nRW 31
1:Only non-default values need be set
Default value of the nRESET_OUT pin after hardware reset
30
1 strap_reset_outb_def_value internal(Hard coded)
After hardware reset, the nRESET_OUT will change to 1(deasserted)
EBI_addr24
0 strap_test_debug_en_1 29 Test debug mode select
0 strap_test_debug_en_0 EBI_addr25 28 Security related(2 bits)? default=0
0 e R e s v r d e N A / 27 e R e s v r d e b t i u m t s e b
0 strap_33_27_mhz_clock internal(Hard coded) 26 33MHz clock is used
0 Reserved N/A 25 Reserved bit must be written with 0. A read returns an unknown value
0 strap_xtal_sel Refer to 24 XTAL select
pin ALT_XTAL_SEL
0 strap_xtal_adj_3 I2S_DATA2 23 XTAL adjustment
0 strap_xtal_adj_2 I2S_DATA3 22
0 strap_xtal_adj_1 21
0 strap_xtal_adj_0 20
1 strap_ebi_rom_size_1 NAND_nRE 19 NOR ROM(always 64MB window): NAND ROM:
0 strap_ebi_rom_size_0 NAND_CLE 18 0=NOR flash
1=OneNAND flash
2=reserved
3=reserved
0 s r t p a e _ i b i _ v n r e _ t d a r d USB0_PWRON 17 = 0 o D n t o n i e v t r E I B a
1=invert upper bits of EBI address(not used by NAND flash)
0 Reserved N/A 16 Reserved bit must be written with 0. A read returns an unknown value
0 Reserved N/A 15
0 strap_pci_ext_arb internal(Hard coded) 14 internal Arb.(default)
0 strap_flash_width EBI_nWE0 13 NOR ROM: NAND ROM:
0=8bit 0=allow writes to block 0
1=16bit 1=ignor write commands to block 0(disallow writes)
0 strap_system_big_endian I2S_S_DATA 12 0:system is LITTLE endian
1:system is BIG endian
0 strap_ebi_cs_swap internal(Hard coded) 11 0=no swap
1=swap cs_0 and cs_1
1 t s a r _ p a n d n f _ a l h s EBI_nWE1 0 1 = 0 o B t o r f m o N R O
1=Boot from NAND
0 strap_spi_slave_enable PCI_nGNT0 9 0=The slave serial port(SSP) uses BSC protocol
1=The SSP uses SPI protocol
0 strap_pci_memwin_size_1 internal(Hard coded) 8 1024MB
internal(Hard coded)
1 strap_pci_memwin_size_0 7
strap_pci_memwin2_en
0 internal(Hard coded) 6 PCI memory window 2 is disabled
0 strap_pci_memwin1_en internal(Hard coded) 5 PCI memory window 1 is enabled
0 strap_pci_client NAND_ALE 4 0=Chip is a PCI master device
1=Chip operates as a PCI slave device
0 Reserved N/A 3 Reserved bit must be written with 0. A read returns an unknown value
0 Reserved N/A 2
0 Reserved N/A 1
1 strap_reset_ext_mode AUD0_SPDIF 0 0=nRESET_OUT is not extended
1=nRESET_OUT is extended 200ms
VCC_3V3
R584 R583 R585 R591 R522
R586 R5E9 R582 R587
10k OPEN OPEN OPEN OPEN 10k OPEN OPEN 10k
EBI_nRW
NAND_nRE
NAND_CLE
EBI_nWE0
EBI_nWE1
NAND_ALE
UART_TX2
UART_TX1
UART_TX0
R531 R589
R533 R521 R581 R572 R552 R592 R5D5 R539 R5D7 R534
OPEN 10k 10k 10k OPEN 10k 10k 10k 10k OPEN 10k
10k
DGND
These configuration resistors do not need to be close to the BCM7601.
So place them at the destination of the trace.
w i r t t n e i w h t . 0 A e r d a r t e r u s n n a u k n o n n w v l a e u
0=disable ECC
1=1 bit ECC
2=4 bit ECC
3=8 bit ECC
d d e r s s
R577 R576
R535 R578
10k OPEN 10k OPEN
R537 R573 R5E0 R575 R574
10k OPEN 10k OPEN 10k
2009.2.16
5. BCM7601-1