Bcm7602-2 Circuit Diagram - LG BD390 Service Manual

2. BCM7601-2 CIRCUIT DIAGRAM
3:B2;3:B5
DDR2_0_ADDR[0-13]
3:C3;3:C6 DDR2_0_BA0
3:C3;3:C6 DDR2_0_BA1
3:C3;3:C6 DDR2_0_BA2
3:F2
DDR2_0_DATA[0-31]
DDR2_0_DQM0
3:C3
3:C3 DDR2_0_DQM1
3:C7
DDR2_0_DQM2
3:C6 DDR2_0_DQM3
3:E4 DDR2_0_DQS0_P
3:E4 DDR2_0_DQS0_N
3:E4 DDR2_0_DQS1_P
DDR2_0_DQS1_N
3:E4
3:E7 DDR2_0_DQS2_P
3:E7 DDR2_0_DQS2_N
3:E7 DDR2_0_DQS3_P
3:E7
DDR2_0_DQS3_N
3:C3;3:C6 DDR2_0_nRAS
3:C3;3:C6 DDR2_0_nCAS
3:C3;3:C6 DDR2_0_nWE
3:B4;3:C3 DDR2_0_CLK01_P
3:B4;3:C3 DDR2_0_CLK01_N
3:B7;3:C6 DDR2_0_CLK23_P
3:B7;3:C6
DDR2_0_CLK23_N
3:C3;3:C6 DDR2_0_CKE
3:C3
DDR2_0_nCS0
3:C6 DDR2_0_nCS1
3:E3;3:E6 DDR2_0_ODT
3:G2;3:G5
DDR2_1_ADDR[0-13]
3:G3;3:G6 DDR2_1_BA0
3:G3;3:G6 DDR2_1_BA1
VCC_1V8
3:G3;3:G6 DDR2_1_BA2
R227
DDR2_1_VREF
1k(1%)
R228 C279 C280
22uF
1k(1%) 0.1uF
DGND
VCC_1V8
place C279 to N3 ball of 7601
place C217 to AE10 ball of 7601
R224
DDR2_0_VREF
1k(1%)
R217 C217 C278
22uF
1k(1%) 0.1uF
DGND
IC201
BCM7601 BGA 507Pin (21 x 21) Broadcom
DDR2_0_ADDR[0] P5 D24
DDR2_0_ADDR_00 EBI_nTS
K2
DDR2_0_ADDR[1] DDR2_0_ADDR_01 C23
EBI_nDS
DDR2_0_ADDR[2] N7 G21
DDR2_0_ADDR_02 EBI_nRD
DDR2_0_ADDR[3] J2 F21
DDR2_0_ADDR_03 EBI_nWE1
DDR2_0_ADDR[4] L4
DDR2_0_ADDR_04 C25
EBI_nWE0
DDR2_0_ADDR[5] H1 J19
DDR2_0_ADDR_05 EBI_nRW
DDR2_0_ADDR[6] K5
DDR2_0_ADDR_06 C24
EBI_nCS3
DDR2_0_ADDR[7] J3 E22
DDR2_0_ADDR_07 EBI_nCS2
M5
DDR2_0_ADDR[8] DDR2_0_ADDR_08 J20
EBI_nCS1
DDR2_0_ADDR[9] H2 K20
DDR2_0_ADDR_09 EBI_nCS0
DDR2_0_ADDR[10] K1 E23
DDR2_0_ADDR_10 EBI_ADDR25
DDR2_0_ADDR[11] K4
DDR2_0_ADDR_11 D23
EBI_ADDR24
DDR2_0_ADDR[12] H3 H20
DDR2_0_ADDR_12 EBI_NAND_RB
DDR2_0_ADDR[13] J5
DDR2_0_ADDR_13 P25
PCI_nGNT0
M2 N25
DDR2_0_BA0 PCI_nREQ0
L3
DDR2_0_BA1 T25
PCI_INT_A0
M3 M24
DDR2_0_BA2 PCI_nRST
DDR2_0_DATA[0] AB7 N23
DDR2_0_DATA_00 PCI_nSERR
DDR2_0_DATA[1] AA4 R19
DDR2_0_DATA_01
PCI_nPERR
DDR2_0_DATA[2] AC4 M23
DDR2_0_DATA_02 PCI_CLK_IN
DDR2_0_DATA[3] AB4
DDR2_0_DATA_03 T24
PCI_nFRAME
DDR2_0_DATA[4] AB5 H22
DDR2_0_DATA_04 PCI_nTRDY
DDR2_0_DATA[5] AC1
DDR2_0_DATA_05 N20
PCI_nDEVSEL
DDR2_0_DATA[6] AA5 L23
DDR2_0_DATA_06 PCI_nSTOP
DDR2_0_DATA[7] AC5 P23
DDR2_0_DATA_07 PCI_nIRDY
DDR2_0_DATA[8] AA7 M20
DDR2_0_DATA_08
PCI_PAR
DDR2_0_DATA[9] W3 K21
DDR2_0_DATA_09 PCI_CBE03
DDR2_0_DATA[10] Y6
DDR2_0_DATA_10 R20
PCI_CBE02
DDR2_0_DATA[11] Y5 H24
DDR2_0_DATA_11 PCI_CBE01
W6
DDR2_0_DATA[12] DDR2_0_DATA_12 J21
PCI_CBE00
DDR2_0_DATA[13] AA3 R21
DDR2_0_DATA_13 PCI_AD31
DDR2_0_DATA[14] Y3 DDR2_0_DATA_14 K25
PCI_AD30
DDR2_0_DATA[15] AA2 L21
DDR2_0_DATA_15 PCI_AD29
DDR2_0_DATA[16] V2 N19
DDR2_0_DATA_16 PCI_AD28
DDR2_0_DATA[17] V5
DDR2_0_DATA_17 K24
PCI_AD27
DDR2_0_DATA[18] W4 P21
DDR2_0_DATA_18 PCI_AD26
DDR2_0_DATA[19] W5
DDR2_0_DATA_19 P20
PCI_AD25
DDR2_0_DATA[20] U7 N22
DDR2_0_DATA_20 PCI_AD24
DDR2_0_DATA[21] V4
DDR2_0_DATA_21 L20
PCI_AD23
DDR2_0_DATA[22] U5 J22
DDR2_0_DATA_22 PCI_AD22
DDR2_0_DATA[23] V1 M19
DDR2_0_DATA_23 PCI_AD21
DDR2_0_DATA[24] T5
DDR2_0_DATA_24 J23
PCI_AD20
DDR2_0_DATA[25] R5 L22
DDR2_0_DATA_25 PCI_AD19
DDR2_0_DATA[26] T3
DDR2_0_DATA_26 E25
PCI_AD18
DDR2_0_DATA[27] R7 D25
DDR2_0_DATA_27 PCI_AD17
DDR2_0_DATA[28] R6
DDR2_0_DATA_28 G22
PCI_AD16
DDR2_0_DATA[29] U6 F23
DDR2_0_DATA_29 PCI_AD15
DDR2_0_DATA[30] P2 G23
DDR2_0_DATA_30 PCI_AD14
DDR2_0_DATA[31] T6
DDR2_0_DATA_31 F25
PCI_AD13
AA6 K23
DDR2_0_DM_0 PCI_AD12
W7
DDR2_0_DM_1 R22
PCI_AD11
V7 R23
DDR2_0_DM_2 PCI_AD10
P1
DDR2_0_DM_3 F24
PCI_AD09
AC2 T23
DDR2_0_DQS_0_P PCI_AD08
AC3 J25
DDR2_0_DQS_0_N PCI_AD07
Y1 H23
DDR2_0_DQS_1_P
PCI_AD06
Y2 H25
DDR2_0_DQS_1_N PCI_AD05
U4
DDR2_0_DQS_2_P L19
PCI_AD04
U3 P24
DDR2_0_DQS_2_N PCI_AD03
R4
DDR2_0_DQS_3_P N21
PCI_AD02
R3 M22
DDR2_0_DQS_3_N PCI_AD01
N4 M25
DDR2_0_nRAS PCI_AD00
N6 W8
DDR2_0_nCAS
DDR2_1_TESTOUT
M1 AB11
DDR2_0_nWE DDR2_1_ODT
AB1
DDR2_0_CLK01_P W10
DDR2_1_ZQ
AB2 AE10
DDR2_0_nCLK01_N DDR2_1_VREF
T1
DDR2_0_CLK23_P AA11
DDR2_1_CS1
T2 W12
DDR2_0_nCLK23_N DDR2_1_CS0
N2 DDR2_0_CKE AD10
DDR2_1_CKE
P7 AB13
DDR2_0_CS0 DDR2_1_nCLK23_N
P4 AC13
DDR2_0_CS1 DDR2_1_CLK23_P
DDR2_0_VREF N3
DDR2_0_VREF AB19
DDR2_1_nCLK01_N
R225 243(1%) J4 AC19
DDR2_0_ZQ DDR2_1_CLK01_P
DGND N5
DDR2_0_ODT AD9
DDR2_1_nWE
L5 Y11
DDR2_0_TESTOUT DDR2_1_nCAS
AC10 DDR2_1_ADDR_00
DDR2_1_ADDR[0] AC9
DDR2_1_nRAS
DDR2_1_ADDR[1] AC6 AD13
DDR2_1_ADDR_01 DDR2_1_DQS_3_N
DDR2_1_ADDR[2] AA10 DDR2_1_ADDR_02 AE12
DDR2_1_DQS_3_P
DDR2_1_ADDR[3] AD6
DDR2_1_ADDR_03 AB15
DDR2_1_DQS_2_N
DDR2_1_ADDR[4] AB9 AC15
DDR2_1_ADDR_04 DDR2_1_DQS_2_P
DDR2_1_ADDR[5] AE6
DDR2_1_ADDR_05 AD18
DDR2_1_DQS_1_N
DDR2_1_ADDR[6] Y10 AE18
DDR2_1_ADDR_06 DDR2_1_DQS_1_P
DDR2_1_ADDR[7] AD5
DDR2_1_ADDR_07 AD20
DDR2_1_DQS_0_N
DDR2_1_ADDR[8] AA9 AD21
DDR2_1_ADDR_08 DDR2_1_DQS_0_P
DDR2_1_ADDR[9] AD4 AB12
DDR2_1_ADDR_09 DDR2_1_DM_3
DDR2_1_ADDR[10] AC7
DDR2_1_ADDR_10 AE14
DDR2_1_DM_2
DDR2_1_ADDR[11] Y9 Y17
DDR2_1_ADDR_11 DDR2_1_DM_1
DDR2_1_ADDR[12] AE4
DDR2_1_ADDR_12 AB20
DDR2_1_DM_0
DDR2_1_ADDR[13] Y8 W13
DDR2_1_ADDR_13 DDR2_1_DATA_31
AE8
DDR2_1_BA0 AC11
DDR2_1_DATA_30
AB8 Y15
DDR2_1_BA1 DDR2_1_DATA_29
AD8 AA13
DDR2_1_BA2 DDR2_1_DATA_28
DDR2_1_DATA[0] W20 Y13
DDR2_1_DATA_00
DDR2_1_DATA_27
DDR2_1_DATA[1] AA19 DDR2_1_DATA_01 AD12
DDR2_1_DATA_26
DDR2_1_DATA[2] Y19
DDR2_1_DATA_02 AA12
DDR2_1_DATA_25
DDR2_1_DATA[3] AA18 DDR2_1_DATA_03 Y14
DDR2_1_DATA_24
DDR2_1_DATA[4] AA20 DDR2_1_DATA_04
AA16
DDR2_1_DATA_23
DDR2_1_DATA[5] W19 AA14
DDR2_1_DATA_05 DDR2_1_DATA_22
DDR2_1_DATA[6] AE20 DDR2_1_DATA_06 AD16
DDR2_1_DATA_21
DDR2_1_DATA[7] Y18 AD14
DDR2_1_DATA_07
DDR2_1_DATA_20
DDR2_1_DATA[8] AB17 DDR2_1_DATA_08 W16
DDR2_1_DATA_19
DDR2_1_DATA[9] AE16 DDR2_1_DATA_09 AA15
DDR2_1_DATA_18
DDR2_1_DATA[10] AA17 DDR2_1_DATA_10 W15
DDR2_1_DATA_17
AB16 DDR2_1_DATA_11
DDR2_1_DATA[11] AC14
DDR2_1_DATA_16
DDR2_1_DATA[12] AC17 DDR2_1_DATA_12 AC18
DDR2_1_DATA_15
DDR2_1_DATA[13] W17 DDR2_1_DATA_13 AD17
DDR2_1_DATA_14
1) a. DQS pairs will eventually have length matching rule to their respective byte lane data
b. CK pairs will eventually have length matching rule to the address lines
2) The decaps and VREF resistors and caps should be laid out near the associated balls. For 7440 they should be
backside in the depopulated ring. VREF is the most sensitive net (in terms of isolation) to route.
3) use top and bottom layers only.
4) Lay out escape plan per attached sketch
5) Complete the layout of the wires in the following order, keeping signals on their layer as much as possible:
CK pairs
DQS diff pairs
DQ and DM
remaining signals
6) Signals can be freely substituted within the following groups: [RS] if this is done, the schematic should be updated to match
DQ[7:0] DQ[15:8]
7) Diff pairs should be routed together 4 mil etch 4 mil spacing
8) Signals should be routed 4 mil etch 4 mil space min, 8 mil spacing mostly.
9) Keep data lines separate from address lines, to avoid x-talk between the two
10) Prepare wire length report and schedule a review
11) LENGTH RULE: Data bits DDR2_n_DATA[31:0] <= 1.5"
12) Keep decoupling caps on back side out from beneath backing plate.
13) Route clocks as differential pairs - Match differential impedance
60 Ohm to plane,
120 Ohm on pair
VCC_1V2
DGND
4:B2;5:H6
NAND_CLE
NAND_ALE 4:B2;5:H6
4:B2;5:H6
NAND_nRE
EBI_nWE1 5:H6
EBI_nWE0 4:B2;5:H6
EBI_nRW 5:H6
TP201
TP202
EBI_nCS1 4:A2
4:A2
EBI_nCS0 EBI_ADDR[25]
EBI_ADDR[24]
EBI_NAND_RB 4:B3
PCI_nGNT0 5:H6
10K R230
EBI_ADDR[24-25]
10K R231
TP203
10K VCC_3V3 5:H6
R232
10K R233
CLK33_OUT_PCI_CLK_IN 5:C3
10K R234
10K R235
10K R236
10K R237
10K R238
TP204
EBI_DATA[7]
EBI_DATA[6]
EBI_DATA[5]
EBI_DATA[4]
EBI_DATA[3]
EBI_DATA[2]
EBI_DATA[1]
EBI_DATA[0]
4:B1
DDR2_1_ODT 3:J3;3:J6 EBI_DATA[0-7]
243(1%) R226
DGND
DDR2_1_nCS1 3:G6
DDR2_1_nCS0 3:G3
DDR2_1_CKE 3:G3;3:G6
DDR2_1_CLK23_N 3:G6;3:G7
DDR2_1_CLK23_P 3:G6;3:G7
DDR2_1_CLK01_N 3:G3;3:G4
DDR2_1_CLK01_P 3:G3;3:G4
DDR2_1_nWE 3:G3;3:G6
DDR2_1_nCAS 3:G3;3:G6
DDR2_1_nRAS
3:G3;3:G6
DDR2_1_DQS3_N 3:J7
DDR2_1_DQS3_P 3:J7
DDR2_1_DQS2_N 3:J7
DDR2_1_DQS2_P 3:J7
DDR2_1_DQS1_N 3:I4
3:I4
DDR2_1_DQS1_P
DDR2_1_DQS0_N 3:I4
DDR2_1_DQS0_P 3:I4
DDR2_1_DQM3 3:G6
DDR2_1_DQM2 3:G7
DDR2_1_DQM1 3:G3
DDR2_1_DQM0 3:G3
DDR2_1_DATA[31]
DDR2_1_DATA[30] DDR2_1_DATA[0-31]
3:K2
DDR2_1_DATA[29]
DDR2_1_DATA[28]
DDR2_1_DATA[27]
DDR2_1_DATA[26]
DDR2_1_DATA[25]
DDR2_1_DATA[24]
DDR2_1_DATA[23]
DDR2_1_DATA[22]
DDR2_1_DATA[21]
DDR2_1_DATA[20]
DDR2_1_DATA[19]
DDR2_1_DATA[18]
DDR2_1_DATA[17]
DDR2_1_DATA[16]
DDR2_1_DATA[15]
DDR2_1_DATA[14]
DDR2 SDRAM LAYOUT GUIDE
DQ[23:16] DQ[31:24]
3-79 3-80
VCC_1V8
DGND
VCC_3V3 VCC_2V5
DGND DGND
IC201
BCM7601 BGA 507Pin (21 x 21) Broadcom
VCC_3V3
G8 VDD33
G16 L15
VDD33 OBSERV_VSS
A17 VDD33 L14
OBSERV_VDD12
F19 E18
VDD33 RMX_PAUSE0
VCC_2V5
K19 VDD33 E19
RMX_SYNC0
P19 D19
VDD33 RMX_DATA0
W21 C19
VDD33 RMX_CLK0
F22
VDD33 PKT_SYNC2 C18
K22 B18
VDD33 PKT_DATA2
P22
A18
VDD33 PKT_CLK2
B24 D17
VDD33 PKT_SYNC1
G12 C17
REG_VDD33 PKT_DATA1
VCC_1V8 F14 B17
REG_OUT_2P5 PKT_CLK1
0 R229 AC24 G17
OTP_V2P5 PKT_SYNC0
K3
PKT_DATA0 F17
VDD18
P3 E17
VDD18 PKT_CLK0
C281
V3 F20
VDD18 SC_VCC_0
AB3 E20
VDD18 SC_PRES_0
0.1uF T7 D20
VDD18 SC_RST_0
Y7 C21
VDD18 SC_CLK_0
AC8 B21
VDD18 SC_IO_0
DGND W9
NC F2
VDD18
AC12 E2
VDD18 NC
W14
VCC_1V2 A22
VDD18 NC
AC16 C20
VDD18 NC
W18 B20
VDD18 NC
AC20 A23
VDD18 NC
F6 C11
VDD12 NC
M10
VDD12 NC B10
N10 AE23
VDD12 NC
P10
AE22
VDD12 NC
M11 AD24
VDD12 NC
N11 AD23
VDD12 NC
P11 AD22
VDD12 NC
K12 AC25
VDD12 NC
L12
VDD12 NC E1
R12 AC23
VDD12 NC
T12
AC21
VDD12 NC
K13 AE3
VDD12 NC
L13
AD3
VDD12 NC
R13 W11
VDD12 NC
T13 U2
VDD12 NC
K14 M7
VDD12 NC
R14 L7
VDD12 NC
T14
NC M6
VDD12
M15 L6
VDD12 NC
N15
K6
VDD12 NC
P15 J6
VDD12 NC
M16 H6
VDD12 NC
N16 H5
VDD12 NC
P16 G3
VDD12 NC
J1
NC G7
VSS
N1 G18
VSS NC
U1 F18
VSS NC
AA1 E21
VSS NC
AD2 F12
VSS NC
H4 F9
VSS NC
M4 E9
VSS NC
T4
NC E5
VSS
Y4 E6
VSS NC
AE5
NC D6
VSS
P6 D5
VSS NC
V6 Y24
VSS VSS
AB6 U24
VSS VSS
AA8 N24
VSS VSS
AE9
VSS VSS J24
K10 E24
VSS VSS
L10
VSS AB22
VSS
R10 AE21
VSS VSS
T10 T21
VSS VSS
AB10 M21
VSS VSS
K11 H21
VSS VSS
L11 D21
VSS VSS
R11 A21
VSS VSS
T11
VSS Y20
VSS
M12 AB18
VSS VSS
N12
VSS D18
VSS
P12 AE17
VSS
VSS
Y12 VSS Y16
VSS
M13 T16
VSS
VSS
N13 VSS R16
VSS
P13
VSS L16
VSS
AE13 VSS K16
VSS
M14
VSS T15
VSS
N14 R15
VSS VSS
P14 VSS K15
VSS
AB14 D15
VSS
VSS
DGND
2009.2.16
2. BCM7601-2
DGND