Texas Instruments ADS8353-Q1 User Manual page 26

Evaluation module
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Bill of Materials, Printed-Circuit Board Layout, and Schematics
7.3 Schematics
External Reference (Default - DNP)
VA
U8
4
IN
DNP
C32
DNP
1uF
3
ENABLE
REF3425IDBVR
GND
VA
R38
DNP
C40
DNP
16V
0
0.1uF
VA
GND
U9
4
1
R42
REFIO_A
V+
DNP
DNP
REF_IN
3
0
V-
OPA320AQDBVRQ1
DNP
C38
16V
0.1uF
GND
GND
EEPROM
EVM_ID_PWR
U6
1
A0
VCC
2
A1
WP
3
A2
SCL
4
VSS
SDA
EEPROM_8P
GND
26
ADS8353Q1EVM-PDK Evaluation Module
6
R48
REF_IN
OUT_F
DNP
1.00k
5
OUT_S
R45
DNP
0.22
2
GND_S
1
GND_F
DNP
C34
10uF
GND
VA
GND
R40
DNP
C41
DNP
16V
0
0.1uF
VA
GND
U10
4
1
R43
REFIO_B
V+
DNP
DNP
REF_IN
3
0
V-
OPA320AQDBVRQ1
DNP
C39
16V
0.1uF
GND
GND
Origin pg 1, conn J1
Origin pg 1, conn J1
EVM_ID_PWR
EVM_ID_PWR
C35
16V
WP
R46
8
0.1uF
GND
10.0k
JP5
WP
7
6
EVM_ID_SCL
C36
GND
5
EVM_ID_SDA
16V
GND
0.1uF
Origins pg 1, conn J1
GND
Figure 7-5. Schematic Diagram (Page 1) of the ADS8353-Q1EVM PCB
Copyright © 2023 Texas Instruments Incorporated
Positive Supply
Connected pg 1,
conn J1
EVM_REG_5V5
LDO_IN_5V5
R47
0
C37
10V
10uF
GND
R49
0
R50
DNP
0
R51
DNP
0
R52
0
R53
DNP
0
R54
DNP
0
GND
Power
Origin Positive
Supply section
Origin pg 1, conn J1
TP17
LDO_IN_5V5
VA
DVDD
V-
5016
TP18
TP19
TP20
TP5
5016
GND
5016
5016
5016
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U7
VA
15
1
IN
OUT
16
20
IN
OUT
13
3
EN
SENSE/FB
R33
0.1
14
C31
NR
4
25V
6P4V2
5
19
1µF
6P4V1
NC
C33
6
18
3P2V
NC
47uF
8
17
1P6V
NC
9
2
0P8V
NC
10
GND
0P4V
11
7
0P2V
GND
12
21
0P1V
PAD
GND
TPS 7A4701QRG WTQ1
GND
LDO_IN_5V5
R55
10.0k
D1
APT2012LZGCK
Green
GND
SBAU327A – JANUARY 2019 – REVISED APRIL 2023
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