Table of Contents
Advertisement
LC-26GA5E
LC-32GD9E
LC-32GA5E
LC-37GD9E
STi5516
2.6.2. Pin Description (Continued)
Table 9: EMI pins
Pin
NOT_EMIRAS or
a
NOT_CI_IORD
NOT_EMICAS or
a
NOT_CI_IOW
NOT_EMICSA
NOT_EMICSB
NOT_EMICSC
NOT_EMICSD
NOT_EMICSE
NOT_EMICSF
NOT_EMIBE[1:0]
NOT_EMIOE or
NOT_CI_OE
NOT_EMILBA or
NOT_CI_WEA
EMIWAITNOTTREADY
EMIRDNOTWR
EMIDATA[15:0]
EMIADDR[25:2]
NOT_EMIREQGNT
NOT_EMIACKREQ
EMIBOOTMODE0
EMISDRAMCLK
EMIFLASHCLK
a. Or equivalent ATA HDD interface signal.
b. 5 V tolerant
c. B3, A3, A4, B4, C4, A5, B5, C5, A6, B6, C6, D6, A7, B7, C7 and A8.
d. EMIADDR[19:20] are used as ATA HDD interface function: ATA CS0 and CS1. There is no
interconnect configuration control register bit to select this function. The addresses are just
reused as chip selects.
e. B8, C8, A9, B9, C9, D9, A10, B10, C10, A11, B11, C11, A12, B12, C12, D12, A13, B13, C13,
D13, A14, B14, C14 and D14.
Location
J2
J1
K4
K3
K2
K1
L4
L3
L1, L2
M1
N3
N4
b
N2
c
d
e
J3
b
H1
H3
b
A1
A2
I/O
Function
O
Row address strobe for SDRAM
O
Column address strobe for SDRAM
O
Peripheral chip select A
O
Peripheral chip select B
O
Peripheral chip select C
O
Peripheral chip select D
O
Peripheral chip select E
O
Peripheral chip select F
O
External device data bus byte enable. 1 bit per
byte of the data bus.
O
External device output enable.
O
Flash device load burst address.
I
External memory device target ready indicator
O
External read/write access indicator. Common to
all devices.
I/O
External common data bus.
O
External common address bus
O
Bus request/grant indicator
I
Bus grant/request indicator
I
External power-up port size indicator
O
SDRAM clock
O
Peripheral clock
90
7368868E
STMicroelectronics Confidential
Pin list
Pad
type
C4
E8
E8
E8
E8
E8
E8
E8
E8
E8
E8
C4
E8
E8
E8
E8
C4
C4
E8
E8
31/709
Advertisement
Table of Contents
