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ADVANCE INFORMATION
Volume 1: General Description
DEN - Digital video inputs Enable
This is the enable signal for the Digital Video Inputs.
DHS - Digital video inputs Horizontal Sync
This is the H Sync signal for the Digital RGB input bus
or for the VGA Video Inputs.
DVS - Digital video inputs Vertical Sync
This is the V Sync signal for the Digital RGB input bus
or for the VGA Video Inputs.
DCLK - Digital video inputs Clock
This is the Clock signal for the Digital Video Inputs.
CLKOUT − Digital Output clock
This is a 20MHz clock for the external video ICs.
VIN 1–22 − Analog Video Input
These are the 19 analog video inputs.
(Vin 4,10 and 14 are missing)
A CVBS, S-VHS, YCrCb or RGB signal is converted
using the luma, chroma and component AD converter.
Vin 8,18 are fast blank inputs. Vin22 is an Hsync input.
The input signals must be AC-coupled.
VOUT 1-3 − Analog Video Output
The analog video inputs that are selected by the video
matrix are output at these pins.
ROUT, GOUT, BOUT − Analog RGB Output
These pins are the analog Red/Green/Blue outputs of
the back-end.
SVMOUT − Scan Velocity Modulation Output
This output delivers the analog SVM signal. The D/A
converter is a current sink like the RGB D/A convert-
ers. At zero signal the output current is 50% of the
maximum output current.
2.2.2.4 Controller Pins
3.13.4.Controller Pins
XTALIN Crystal Input and XTALOUT Crystal Output
These pins are connected to an 20.25 MHz crystal
oscillator. An external clock can be fed into XTALIN.
RESETQ − Reset Input/Output
A low level on this pin resets the VCT 69xyP. The
internal CPU can pull down this pin to reset external
devices connected to this pin.
TEST − Test Input
This pin enables factory test modes. For normal opera-
tion, it must be connected to ground.
2
SCL − I
C Bus Clock
2
This pin delivers the I
C bus clock line. The signal can
be pulled down by external slave ICs to slow down
data transfer.
Micronas
SDA − I
This pin delivers the I
P1_0−P1_3 − I/O Port
These pins provide CPU controlled I/O ports.
P1_4−P1_7 − I/O Port
These pins provide CPU controlled I/O ports.
Also used as CADC1−4 − Controller A/D inputs 1 to 4.
This 4 pins are analog/digital converters from the con-
troller
P2_0−P2_7 − I/O Port
These pins provide CPU controlled I/O ports.
P3_0−P3_7 − I/O Port
These pins provide CPU controlled I/O ports.
P4_0−P4_7 − I/O Port
These pins provide CPU controlled I/O ports.
TDO-TCLK-TDI-TMS -JTAG Interface Pins for TV con-
troler.
TCLK at pin 4 (656O3) has during reset an internal pull
up: (TCLK=0) at end of reset enables the JTAG mode
at 656 LSB's, this can also be done via I2C.
This JTAG is also available at Port(1 and 2) but only
via I2C.
TDOFW-TCLKFW-TDIFW-TMSFW -JTAG Interface
Pins for firmware controler.
TCLKFW at pin 208 (656O7) has during reset an inter-
nal pull up: (TCLKFW=0) at end of reset enables the
JTAG mode, this can also be done via I2C.
77
November 3, 2004;
6251-644-1-1AI
2
C Bus Data
2
C bus data line.
VCT 69xyP
LC-26GA5E
LC-32GD9E
LC-32GA5E
LC-37GD9E
1-67
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