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QT-MP3W
77
U711 92L31003980031 : FLASH MEMORY ( SST39VF800A )
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
NC
NC
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
Memory Address
PIN DESCRIPTION
Symbol
Pin Name
1
A
A
Address Inputs
-
MS
0
DQ
DQ
Data Input/output
-
15
0
CE#
Chip Enable
OE#
Output Enable
WE#
Write Enable
V
Power Supply
DD
V
Ground
SS
NC
No Connection
1.
A
=
Most significant address
MS
A
=
A
for SST39LF/VF200A,
MS
16
1
2
3
4
5
6
7
8
9
10
11
12
SST39LF / VF800A
13
14
15
16
17
18
19
20
21
22
23
24
Address Buffer & Latches
CE#
OE#
Control Logic
WE#
Figure 7-4 BLOCK DIAGRAM OF IC
Functions
To provide memory addresses. During Sector-Erase
sector. During Block-Erase
A
A
-
MS 15
To ouput data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide power supply voltage:
Unconnected pins.
A
for SST39LF/VF400A, and
17
X-Decoder
I/O Buffers and Data Latches
A
A
address lines will select the
-
MS 11
address lines will select the block.
3.0-3.6V for SST39LF200A/400A/800A
2.7-3.6V for SST39VF200A/400A/800A
A
for SST39LF/VF800A
18
7 – 6
A16
48
47
NC
46
V SS
45
DQ15
44
DQ7
43
DQ14
42
DQ6
41
DQ13
40
DQ5
DQ12
39
38
DQ4
37
V DD
36
DQ11
35
DQ3
34
DQ10
33
DQ2
32
DQ9
31
DQ1
30
DQ8
29
DQ0
0E#
28
V SS
27
CE#
26
25
A0
SuperFlash
Memory
Y-Decoder
DQ
DQ
-
15
O
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