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QT-MP3W
U710 92L31000250110 : CPU ( TS2501 ) ( 3/4 )
PIN DESCRIPTION
Signal Name
Shared Signal
SD_CKE
GPIO_B[0]
SD_CLK
GPO
SD_nCS
SD_nCLK/
GPIO_B[1]
XA[21:20]
DQM[0:1]
XA[19:18]
DQS[1:0]
XA[17]
ND_CLE
XA[16]
SD_nRAS
XA[15]
SD_nCAS
XA[14]
SD_BA[1]
XA[13]
SD_BA[0]
XA[12:7]
XA[6:0]
XA[15:9]
XA[8:4]
XA[3:0]
NCS[3:0]
ND_nOE[3:0] /
GPIO_B[5:2]
ND_nWE
GPIO_B[7]
nWE
nOE
READY
GPIO_B[0]
SD_CKE
GPIO_D[21:1
FGPIO[14:11] /
8]
CISD[7:4]
GPIO_D[17]
FGPIO[10] / SCL
/ CISHS
GPIO_D[16]
FGPIO[9] / SDA /
CISVS
GPIO_D[15]
FGPIO[9] /
CISCLK
ADIN_0
-
ADIN_2
-
ADIN_4
-
XIN
-
XOUT
-
XFILT
-
XTIN
-
XTOUT
-
MODE1
-
PKG1
-
nRESET
-
TDI
-
TMS
-
TCK
-
TDO
-
nTRST
-
VDDIO
-
VDD_USB
-
Pin #
Type
External Memory Interface Pins
56
I/O
SDRAM Clock Enable signal. Active high. / GPIO_B[0]
44
I/O
SDRAM Clock / GPO. SD_CLK can be used as a general purpose output.
Refer to section "MEMORY CONTROLLER".
(MCFG register Bit[3] and Bit [1])
46
I/O
Chip select signal for SDRAM, Active low / Inverted SD_CLK for DDR SDRAM
/ GPIO_B[1]
43:42
I/O
External Bus Address Bit [21:20] / Data I/O Mask 0, 1
40:39
I/O
External Bus Address Bit [19:18] / DDR SDRAM / GPIO_B[1]
38
I/O
External Bus Address Bit [17] / CLE for NAND Flash
37
I/O
External Bus Address Bit [16] / SDRAM RAS signal / ALE for NAND Flash
36
I/O
External Bus Address Bit [15] / SDRAM CAS signal
35
I/O
External Bus Address Bit [14] / SDRAM Bank Address 1
34
I/O
External Bus Address Bit [13] / SDRAM Bank Address 0
31:26
I/O
External Bus Address Bit [12:0]
23:17
15:9
I/O
External Bus Address Bit [15:0]
6:2
128:125
50:47
I/O
External Bus Chip Select [3:0] / NAND Flash Output Enable [3:0] /
GPIO_B[5:2]
57
I/O
NAND Flash WE. Active low. / GPIO_B[7]
58
I/O
Static Memory Write Enable signal. Active low.
59
I/O
Static Memory Write Output Enable signal. Active low.
73
I
Ready information from external device.
SDRAM / Inverted Clock for DDR SDRAM.
56
I/O
GPIO[0] / SDRAM clock control
96:93
I/O
GPIO_D[21:18] / Fast GPIO bits 14 ~ 11 / Camera Interface Data Inputs
3 ~ 0. Internal pull-up resistors are enabled at reset. GPIO_D[19:18] are
disabled in TS250IT(N.C).
92
I/O
GPIO_D[17] / Fast GPIO bit 10 / 12C SCL / Camera Interface Hsync.
91
I/O
GPIO_D[16] / Fast GPIO bit 9 / 12C SDA / Camera Interface Vsync.
90
I/O
GPIO_D[15] / Fast GPIO bit 8 / Camera Interface Clock
82
AI
General purpose multi-channel ADC input 0
83
AI
General purpose multi-channel ADC input 2
84
AI
General purpose multi-channel ADC input 4
74
I
Main Crystal Oscillator Input for PLL. 12MHz Crystal must be used if USB
Boot Mode is required. Input voltage must not exceed VDD_OSC
(1.95V max).
75
O
Main Crystal Oscillator Output for PLL
78
AO
PLL filter output
69
I
Sub Crystal Oscillator Input. 32.768kHz is recommended. Input voltage must
not exceed VDD_OSC (1.95V max).
70
O
Sub Crystal Oscillator Output
98
I
Mode Setting Input 1. Pull-down for normal operation.
89
I
Package ID1. Pull-up for normal operation.
72
I
System Reset. Active low.
99
I
JTAG serial data input for ARM940T
100
I
JTAG test mode select for ARM940T
101
I
JTAG test clock for ARM940T
102
I/O
JTAG serial data output for ARM940T. External pull-up resistor is required to
prevent floating during normal operation.
103
I
JTAG reset signal for ARM940T. Active low.
112
PWR
Digital Power for I/O (1.8V ~ 3.3V)
76
33
16
64
PWR
Power for USB I/O (3.3V)
Description-TS2501
7 – 4
ADC Input Pins
Clock Pins
Mode Control Pins
JTAG Interface Pins
Power Pins
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