Test Complement Under Mask - Samsung SAM88RCRI S3C9442 Manual

SAM88RCRI INSTRUCTION SET
TCM

— Test Complement Under Mask

TCM dst,src
Operation: (NOT dst) AND src
This instruction tests selected bits in the destination operand for a logic one value. The bits to be
tested are specified by setting a "1" bit in the corresponding position of the source operand
(mask). The TCM statement complements the destination operand, which is then ANDed with the
source mask. The zero (Z) flag can then be checked to determine the result. The destination and
source operands are unaffected.
Flags: C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
Format:
opc
opc
opc
Examples: Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and
register 02H = 23H:
TCM
TCM
TCM
TCM
TCM
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1
the value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register
for a "1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one
and can be tested to determine the result of the TCM operation.
6-48
dst | src
src dst
dst src
→
R0,R1 R0 = 0C7H, R1 = 02H, Z = "1"
→
R0,@R1 R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"
→
00H,01H Register 00H = 2BH, register 01H = 02H, Z = "1"
00H,@01H →
Register 00H = 2BH, register 01H = 02H,
register 02H = 23H, Z = "1"
→
00H,#34 Register 00H = 2BH, Z = "0"
S3C9442/C9444/F9444/C9452/C9454/F9454
Bytes Cycles Opcode
2 4
6
3 6
6
3 6
Addr Mode
(Hex) dst src
62 r r
63 r lr
64 R R
65 R IR
66 R IM