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739942 | 2022.09.21
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5. Development Kits Hardware and Configuration
The development board supports multiple configuration modes as listed in the
following table. The default configuration is AS x4 (Fast) using a 2 Gb QSPI flash
device.
Table 5.
Supported Configuration Modes
Configuration Mode
JTAG
Avalon-ST x16
AS x4 (Fast) (Default)
AS x4 (Normal)
5.1. JTAG Configuration Mode
When
MSEL[2:1]
the configuration mode defaults to JTAG.
5.2. Active Serial (AS) x4 Configuration Mode
The AS x4 configuration mode can be set to either fast or normal mode. When the AS
x4 mode is enabled, the FPGA configures itself after power-on with the programming
file stored within the QSPI flash (U9) connected directly to the FPGA SDM interface. In
this mode, the FPGA downloads its programming bitstream directly from the QSPI
flash device. This is the default configuration mode for the board shipped from the
factory.
5.3. Avalon-ST x16 Configuration Mode
When set to the Avalon-ST x16 mode, the Intel MAX 10 System Controller (U5) acts
as the configuration host to manage configuration download. After power on, the Intel
MAX 10 reads the configuration bitstream programmed into the QSPI flash (U4) and
sends this data to FPGA SDM interface to program the FPGA. The U4 is a 2 Gb QSPI
flash device, allowing for four FPGA images to be stored. Image download selection is
controlled by jumpers J105 and J106 as listed in the following table. The default
image to be programmed is image 0.
Note:
Do not use U3, it is just hardware backup for future use.
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Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the
application or use of any information, product, or service described herein except as expressly agreed to in
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MSEL2 SW3.2
1
1
0
0
are both set to logic high by DIP switch
MSEL1 SW3.2
1
0
0
1
SW3[2:1]
MSEL0 (Pulled high)
1
1
1
1
= [OFF:OFF],
ISO
9001:2015
Registered
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