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Note 1: "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or
specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: Typical values represent most likely parametric norms at V
Conditions at the time of product characterization and are not guaranteed.
Note 4: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except V
ΔV
, which are differential voltages.
OD
Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the supply pins with amplitude = 100 mVp-p measured
at the device V
and V
pins. Bit error rate testing of input to the serializer and output of the deserializer with 10 meter cable shows no error when the noise
DD33
DDIO
frequency is less than 50MHz.
Note 5: Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the V
100 mVp-p measured at the device V
the noise frequency on the Ser is less than 50MHz. The Des on the other hand shows no error when the noise frequency is less than 50 MHz.
Note 6: t
is the time required by the device to obtain lock when exiting power-down state with an active PCLK.
PLD
Note 7: Specification is guaranteed by characterization and is not tested in production
Note 8: Specification is guaranteed by design and is not tested in production
Note 9: t
(@BER of 1E-9) specifies the allowable jitter on RxCLKIN±
TJIT
Note 10: Jitter Frequency is specified in conjunction with DS90UH928Q PLL bandwidth.
Note 11: UI – Unit Interval is equivalent to one ideal serialized bit width. The UI scales with PCLK frequency.
Note 12: Output jitter specs are dependent upon the input clock jitter at the SER
Note 13: The DS90UH927Q V
DD33
a monotonic rise
Note 14: PDB is specified to 3.3V LVCMOS only and must be driven or pulled up to V
Note 15: I
is not specified for an indefinite period of time. Do not hold in short circuit for more than 500ms or part damage may result
OS
Note 16: I2S specifications for t
LC
t
and t
must be longer than the greater of either 0.35*T
LC
HC
Copyright © 1999-2012, Texas Instruments Incorporated
DD33
and V
pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows no error when
DD33
DDIO
and V
voltages require a specific ramp rate during power up. The power supply ramp time must be less than 1.5ms with
DDIO
and t
pulses must each be greater than 2 PCLK periods to guarantee sampling and supersedes the 0.35*T
HC
or 2*PCLK
I2S_CLK
= 3.3V, V
= 1.8V or 3.3V, Ta = +25 degC, and at the Recommended Operation
DDIO
≥
or to V
3.0V
DD33
DDIO
DS90UH927Q
and
OD
and V
supplies with amplitude =
DD33
DDIO
requirement.
I2S_CLK
11
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