Texas Instruments AM335 Series Design Manual page 13

www.ti.com
3.1.3.3 Deep Sleep Voltage Scaling
It is possible to scale the voltages on both the MPU and CORE supply rails down to 0.95 V when in
DeepSleep once powerdomains are shut off. The I2C sequences need to scale voltage varies from board
to board and are dependent on which PMIC is in use, so board-specific binaries are used that are passed
to the CM3 firmware to define the sequences needed during the sleep and wake paths. The CM3 firmware
is then able to write these sequences out at the proper location in the Deep Sleep path on I2C0. It is not
necessary to regenerate this blob if using a power tree based off of an existing TI EVM; however, if the
system has a different PMIC or power management system, it may be necessary to reconfigure this blob
for your specific device. Binary blobs are available for the following AM335x designs:
• am335x-evm-scale-data.bin
– AM335x GP EVM
– AM335x Starterkit
• am335x-bone-scale-data.bin
– AM335x Beaglebone
– AM335x Beaglebone Black
The name of the binary blob used can be configured in the Device Tree and is detailed in the next section.
If a different combination of processor and PMIC are used in a system, it would be necessary to create
your own binary blob in order to enable this functionality.
Scale Data Format
Each binary file contains a small header with a magic number and offsets to the sleep and wake sections.
The sleep and wake sections themselves consist of two bytes to specify the I2C bus speed for the
operation and blocks of bytes that specify the message. The header is 4 bytes long and is shown here:
Size (bytes)
2
1
1
Offsets for sleep and wake data are in bytes starting at the first byte after the header, with the first byte
being counted as 0.
Message structure for each section is as follows:
Size (bytes)
2
1
1
1
1
1
Example Binary Blob and Explanation
### Explanation Of Values ###
0c57 # Magic number
00 # Offset from first byte after header to sleep section
06 # Offset from first byte after header to wake section
0034 # Sleep sequence section, starts with two bytes to describe i2c bus in khz (100)
02 2d 25 1f # Length of message, evm i2c bus addr, then message (i2c reg 0x25, write value 0x1f)
0034 # Wake sequence section, starts with two bytes to describe i2c bus in khz (100)
02 2d 25 2b # Length of message, evm i2c bus addr, then message (i2c reg 0x25, write value 0x2b)
SPRAC74A – February 2017 – Revised March 2017
Submit Documentation Feedback
Field
Magic Number (0x0C57)
Offset to sleep data
Offset to wake data
Field
Bus speed in KHz (little endian)
Message size, counting from first byte after I2C Bus address
I2C Bus address
First byte of message (typically I2C register address)
Second byte of message (typically value to write to register)
Nth byte of message
Copyright © 2017, Texas Instruments Incorporated
Linux Power Optimization Features
AM335x Low Power Design Guide
13