Control Interface; Table 4-7. Vddio Interface Header - J16; Table 4-8. Gpio Interface Header - J22; Table 4-9. Cmlout Output Signals - Texas Instruments DS90UB954-Q1EVM User Manual

DS90UB954-Q1EVM Board Configuration

4.7 Control Interface

Reference
J16
Reference
J22.1
J22.3
J22.5
J22.7
J22.9
J22.11
J22.13
J22.15
Reference
TP16
TP17
Reference
J15.1
J15.2
J15.3
J15.4
(1) Only set one ON.
(2) This function is only available with 2-MP ADAS chipsets.
Reference Signal
J11.1 BISTEN
J11.2 RSVD
J11.3 VDD_SEL
J11.4 PDB
12 DS90UB954-Q1EVM Deserializer User's Guide

Table 4-7. VDDIO Interface Header - J16

Signal
Selects VDDIO bus voltage
VDDIO Short pins 1-2: 3.3V IO (Default)
Short pins 2-3: 1.8V IO

Table 4-8. GPIO Interface Header - J22

Signal
GPIO0 General Purpose Input/Output 0
GPIO1 General Purpose Input/Output 1
GPIO2 General Purpose Input/Output 2
General Purpose Input/Output 3 / Interrupt (Active Low).
GPIO3/INTB
Pulled up to VDDIO by 4.7kΩ
GPIO4 General Purpose Input/Output 4
GPIO5 General Purpose Input/Output 5
GPIO6 General Purpose Input/Output 6
EN 25MHz Enable/Disable 25MHz Oscillator

Table 4-9. CMLOUT Output Signals

Signal
CMLOUTP Test Pad for Channel Monitor Loop-through Driver
CMLOUTN Test Pad for Channel Monitor Loop-through Driver

Table 4-10. FPD-Link III Mode Control- J15

(1)
Mode
1 CSI Mode (DS90UB953-Q1 compatible)
2 RAW12 / LF (DS90UB933 compatible)
3 RAW12 / HF (DS90UB933 compatible)
4 RAW10 (DS90UB933 compatible)

Table 4-11. Device Mode Control - J11

Input = L
For Normal operation (Default)
Tied to GND (Default)
Internal 1.1V regulator from
1.8V supply (Default)
Device is powered down
Copyright © 2022 Texas Instruments Incorporated
Description
Description
Description
Description
(2)
Input = H
Test Mode enable
N/A
1.1V is supplied to VDD1V1
pins
Device is enabled (Default)
SNLU223C – AUGUST 2017 – REVISED NOVEMBER 2022
www.ti.com
Description
Test Mode
Reserved
VDD 1.1V Source Select
Power-down Mode
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