MSI MS-6104 User Manual page 45

Chapter 3 AWARD BIOS USER'S GUIDE
ECC Checking Generation
The system chipset supports Error Code Correct (ECC) checking
and generation. To use this setting the system needs to be used
with a parity bit DRAM module. Disabled is the default setting.
Fast DRAM Refresh
Choosing Disabled (default) will select the normal mode where
the refresh rate is every 15ns. Choosing Enabled will call for a
refresh cycle every 32 host clocks and the system will
implement a refresh cycle every 531ns/480ns for 60MHz and
66MHz respectively.
Read-Around-Write
Choosing Disabled (default) will retire all the DBX before a
CPU or PCI read access is serviced. If Enabled is chosen the
DBX won't retire before a CPU or PCI read access is serviced.
Note: The DBX is Data Bus Accelerator which is one chip of the NATOMA
chipset (Intel 440FX PCIset).
PCI Burst Write Combine
Choosing Enabled (default) allows the DBX to do back to back
sequential CPU to PCI writes (Dword or larger) within a single
PCI write Burst. When Disabled back to back sequential CPU
to PCI writes (Dword or larger) will be split into several single
PCI write cycles.
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