Phase Locked Loop - GE Marquette 418793-001 Service Manual

Phase Locked Loop

6-8
UPPER LEVEL ASSEMBLY: Theory of Operation
The phase-locked loop frequency synthesizer generates a sinusoidal
carrier signal at a programmed frequency as presented in the table below
for modulation by the digital data signal. The phase-locked loop
frequency synthesizer consists of a phase-locked loop section, a passive
loop filter section, and a voltage controlled oscillator section.
Frequencies of the Phase-Locked Loop
VHF U.S.
VHF International
VHF United Kingdom
UHF International
The phase-locked loop (PLL) section (sheet 6) is based upon integrated
circuit U2. A sample of the generated RF carrier signal is applied to the
PLL at the FIN input (pin 10). This sampled signal is phase and
frequency compared to the reference 12.5 kHz signal.
The 10-MHz reference frequency (10 MHz) is generated using Y1 at pins
1 and 3. This reference signal is divided in PLL U2 to 12.5 kHz, which is
set as the frequency tuning step of the frequency synthesizer. The
sampled RF carrier signal is divided using internal prescalers in U2 by
64 or 65 and then divided again by the programmable registers. The data
written to these registers, by the microprocessor, specify the carrier
frequency.
Any error in phase or frequency between the reference signal and the
sampled RF signal is converted to an error signal at the D0 port of the
PLL (pin 6). This error signal is filtered by a loop filter and used as a
tuning voltage for the VCO.
PLL U2 clock, data, and enable inputs (pins 11, 13, and 14) are used to
program the frequency synthesizer to one half the desired carrier
frequency. In addition, lock detect (pin 8) is used to detect if the
synthesizer is on frequency by monitoring the error between the divided
RF input signal and the divided reference signal. Note that the frequency
synthesizer is operated at one half the transmitter's operating frequency.
The loop filter is a type II third-order low-pass filter that filters the error
signal and reference spur content from the synthesizer D0 port. The filter
also converts the error signal to a voltage that controls the VCO
frequency and phase.
Resistor R17 and capacitors C21 and C22 form the type II second-order
loop filter. Resistor R18 and capacitor C23 form a low-pass filter
designed to have 30 dB of attenuation at the reference frequency of 12.5
kHz.
APEX Telemetry Transmitter
401566-166
87.025 to 107.975 MHz
108.00 to 121.00 MHz
86.65, 86.875, 86.925, 86.975 MHz
215.00 to 237.00 MHz
Revision D