Teac AG-D9260 Service Manual page 12

Dolby Digital/Pro Logic DTS DECODER (YSS912C:INPUT IC43)
PIN No. SYM BOL
1,31,71 VDD1
2 RAM CEN
3 RAM A16
4 RAM A15
5 SDIB0
6 SDIB1
7 SDIB2
8 XI
9 XO
10, 30 VSS
11 AVDD
12 SDIB3
13 TEST
14 TEST
15 OVFB
16 DTSDATA
17 AC3DATA
18 SDOB3
19 CPO
20 AVSS
21,41,51,81,91 VDD2
22 SDOA2
23 SDOA1
24 SDOA0
25 ~ 29 RAM A 14~10
32 ~ 35 OPORT 0~3
36 ~ 39 OPORT 4~7
VSS
40,50,60,80,90,100
42 ~ 44 RAAM 9~7
45 ~ 47 SDOB 2~0
48 SDBCK1
49 SDWCK1
52 NONPCM
53 CRC
54 M UTE
55 KARAOKE
56 SURENC
57 /SDBCK 0
58 RAM A6
59 RAM A5
61 RAM A4
62 /IC
63 TEST
64 RAM A3
65 /CSB
66 /CS
67 SO
68 SI
69 SCK
12
I/ O
- +5V Pow er Supply(for I/Os)
O External SRAM interface /CE
O External SRAM interface address 16
O External SRAM interface address 15
I+ PCM input 0 to Sub DSP(not use)
I+ PCM input 1 to Sub DSP(not use)
I+ PCM input 2 to Sub DSP(not use)
I+
Crystal oscillator connection(12.288M Hz)
O
- Ground
- +3.3V pow er supply (for PLL circuit)
I+ PCM input 3 to Sub DSP(not use)
- Test term inal(to be open in norm al use)
- Test term inal(to be open in norm al use)
O Detection of overflow at Sub DSP (not use)
O Detection of DTS data (not use)
O Detection of AC-3 data (not use)
O PCM output from Sub DSP
A Output terminal for PLL,to be connected to ground through the external analog filter circuit
- Ground for PLL circuit)
- +3.3V pow er supply (for core logic)
O PCM output from M ain DSP (C,LFE)
O PCM output from M ain DSP (LS,RS)
O PCM output from M ain DSP (L,R)
O External SRAM interface address 14~10
O Output port for general purpose
O Output port for general purpose (not use)
- Ground
O External SRAM interface address 9~7
O PCM output from Sub DSP
I+ Bit clock input for SDOA,SDIB,SDOB (not use)
I+ Word clock input for SDOA,SDIB,SDOB (not use)
O Detection of non-PCM data (not use)
O Detection of AC-3 CRC error (not use)
O Detection of auto m ute (not use)
O Detection of AC-3 karaoke data (not use)
O Detection of AC-3 2/0 m ode Dolby surround encoded input (not use)
O Inverted SDBCK0 clock output (refer to Block diagram )
O External SRAM interface address 6
O External SRAM interface address 5
O External SRAM interface address 4
Is Initial clear
- Test term inal (to be ofen in norm al use)
O External SRAM interface address 3
Is+ Sub DSP Chip select
Is M icroprocessor interface Chip select input
Ot M icroprocessor interface serial data output
Is M icroprocessor interface /Sub DSP Serial data input
Is M icroprocessor interface /Sub DSP clock input
DESCRIPTION