Watchdog Timer Registers - Asus AAEON EPIC-CFS7-A13-0002 User Manual

B.1

Watchdog Timer Registers

Table 1 : Watch dog relative IO address
Default Value
I/O Base
0x2E
Address
Register
Watchdog
WDTRST#
Enable
Pulse Width
Signal Polarity
Counting Unit
Output Signal
Type
Watchdog
Timer Enable
Timeout Status
Timer Counter
Appendix B – Watchdog Timer Programming
Note
I/O Base address for Watchdog operation.
This address is assigned by SIO LDN7
Table 2 : Watchdog relative register table
Offset BitNum
0x00 7
0x05 0:1
0x05 2
0x05 3
0x05 4
0x05 5
0x05 6
0x06
Value
Enable/Disable
time out
1 WDTRST#
0: Disable
1: Enable
Width of Pulse signal
00: 1ms (do not use)
01: 25ms
01 10: 125ms
11: 5s
Pulse width is must longer
then 16ms.
0: low active
0 1: high active
Must set this bit to 0
Select time unit.
0 0: second
1: minute
0: Level
1 1: Pulse
Must set this bit to 1
0: Disable
1
1: Enable
1: timeout occurred. Write a
1
1 to clear timeout status
Time of watchdog timer
(0~255)
Note
output via
61