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7. Memory Addressing and Expansion
system. The boards use the standard 44-pin, 0.156-inch
center edge connector. The connectors in the
backplane are on 0.6-inch centers. The boards used for
a custom design must be 4.5 inches wide by about 7.5
inches. The Microboard Breadboard CDP18S659 fits
into the eight-card chassis and can accommodate up to
40 integrated circuits, thus lending itself readily to
custom-designed memory modules.
To optimize system performance, all appropriate
CPU signals are wired directly from the CDP1802 to
the backplane. When additional modules are used, the
capacitive loading on all signals should be minimized
by the use of input and output buffers such as types
CD4049, CD4050, CDP1856, CDP1857, orthe like. In
addition, each memory module must latch the high-
order address bits with the TPA trailing edge and
provide the decoding for memory device selection. The
designer should refer to the data booklet for the
CDP1802 (File No. 1023) for timing information. The
timing information should be carefully adjusted to
allow for added loading and circuit delays attributable
to the expansion modules.
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