Texas Instruments TRF7963A Manual page 31

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6.12.5 Data Transmission to MCU
Before beginning data transmission, the FIFO should always be cleared with a reset command (0x0F).
Data transmission is initiated with a selected command (see
reader to do a continuous write command (0x3D) (see
into register 0x1D is the TX length byte 1 (upper and middle nibbles), while the following byte in register
0x1E is the TX length byte 2 (lower nibble and broken byte length). The TX byte length determines when
the reader sends the EOF byte. After the TX length bytes are written, FIFO data is loaded in register 0x1F
with byte storage locations 0 to 11. Data transmission begins automatically after the first byte is written
into the FIFO. The loading of TX length bytes and the FIFO can be done with a continuous write
command, as the addresses are sequential.
At the start of transmission, the flag B7 (IRQ_TX) is set in the IRQ Status register. If the transmit data is
shorter than or equal to 4 bytes, the interrupt is sent only at the end of the transmit operation. If the
number of bytes to be transmitted is higher or equal to 5, then the interrupt is generated. This occurs also
when the number of bytes in the FIFO reaches 3. The MCU should check the IRQ Status register and
FIFO Status register and then load additional data to the FIFO, if needed. At the end of the transmit
operation, an interrupt is sent to inform the MCU that the task is complete.
6.12.6 Serial Interface Communication (SPI)
When an SPI interface is used, I/O pins I/O_2, I/O_1, and I/O_0 must be hard-wired as specified in
Table 6-6. On power up, the TRF7963A looks for the status of these pins; if they are not the same (not all
high, or not all low), the reader enters into one of two possible SPI modes:
• SPI with slave select
or
• SPI without slave select
The choice of one of these modes over the other should be made based on the available GPIOs and the
desired control of the system.
The serial communications work in the same manner as the parallel communications with respect to the
FIFO, except for the following condition. On receiving an IRQ from the reader, the MCU reads the
TRF7963A IRQ Status register to determine how to service the reader. After this, the MCU must to do a
dummy read to clear the reader's IRQ Status register. The dummy read is required in SPI mode, because
the reader's IRQ Status register needs an additional clock cycle to clear the register. This is not required
in parallel mode, because the additional clock cycle is included in the Stop condition.
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SLOS758G – DECEMBER 2011 – REVISED MARCH 2020
6.13). The MCU then commands the
6-7) starting from register 0x1D. Data written
Detailed Description
TRF7963A
31