HP OmniBook 5000 Familiarization Manual page 50

Beep Code Description
none CPU register test in progress or failure.
1-1-1 CPU Failure
1-1-3 CMOS write/read test in progress or failure. Failure will result in a system
halt.
1-1-4 ROM BIOS checksum test in progress or failure. Failure will result in a
system halt. Checksum test - All of the values in a given range of
locations are added together. The range includes a location which, when
added to sum of the ranges, will produce a known result (0). BIOS is in
FLASH and can only be fixed through replacement of the flash device (not
a field repairable item) Customer units should be returned for repair.
1-2-1 Programmable interval timer 0 test in progress or failure. Failure will
result in a system
1-2-2 DMA channel 0 address and count register test in progress or failure.
Failure will result in a system halt.
1-2-3 DMA page register write/read test in progress or failure. Failure will result
in a system halt.
1-3-1 RAM refresh verification test in progress or failure. Failure will result in a
system halt.
1-3-2 SMI RAM Bad. Failure will result in a system halt.
None First 64K RAM test in progress. No specific test is performed - just
indicates that the test is beginning (i.e., no failure).
1-3-3 First 64K RAM chip or data line failure, multi-bit. Failure results in a
system halt.
1-4-2 Parity failure first 64K RAM. Failure results in a system halt.
2-1-1/2/3/4 First 64K RAM chip or data line failure on bit x. Failure results in a system
halt.
2-2-1/2/3/4
2-3-1/2/3/4
2-4-1/2/3/4
3-1-1 Slave DMA register test in progress or failure. Failure results in a system
halt.
3-1-2 Master DMA register test in progress or failure. Failure results in a system
halt.
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