Table of Contents
Advertisement
AM572x IDK EVM design contains 2 clamp circuits that may not be necessary
A.14
AM572x IDK EVM design contains 2 clamp circuits that may not be necessary
During early investigation of power shut-down sequencing, it was determined that clamps were required
on every 3.3V supply to the dual-voltage I/O cell supplies (VDDSHVx). This would enforce the requirement
shown in Figure 5-3 of the
states that the 3.3V supply inputs must never be more than 2.0V above the VDDS18V supply, even during
ramping up or ramping down. The AM572x IDK EVM design contains these clamp circuits on both V3_3D,
that powers almost all VDDSHVx supplies, and VSDMMC, that powers VDDSHV8 used with the SDCARD
on MMC1. Later it was determined that the only method to maintain device reliability was to fully enforce
the supply sequence requirements shown in Figures 5-1 and 5-2 of the
Revision 2.0 Data Manual
shortened shut-down sequence that enforces the DM requirements in a time period (~1ms) that the PMIC
input can hold up the supplies. The PMIC also has supply discharge resistors to pull down the supplies
quickly when they are turning off. These 2 capabilities in the companion PMIC make the clamp circuits
superfluous. However, designs that use REGEN1 to power the VDDSHVx supplies through a power
switch will still need the clamp circuit. The power switches available do not discharge the supplies quick
enough.
A.15
Crystal connected to osc0 needs to have 50 ppm or better long term accuracy
The crystal connected to osc0 needs to have 50ppm or better long term accuracy since it generates
clocks used for Ethernet interfaces. The current crystal has 30ppm accuracy and 50ppm temperature
variation for a combined tolerance of 80ppm. It also has aging of 2ppm per year.
A.16
Software must program the CDCE913 for 0-pf load capacitance
Software must program the CDCE913 for 0pf load capacitance to allow crystals to operate at their target
frequency. Crystal load capacitors can be added to the oscillator circuit to allow the generated clock to
output at the required nominal frequency so that this programming is not required. The default capacitance
within the CDCE913 is 10pF so the capacitors C172, C173, C193, and C194 should be 8pF. Please refer
to the
CDCE(L)913: Flexible Low Power LVCMOS Clock Generator With SSC Support for EMI Reduction
Data Manual (SCAS849)
Ethernet circuitry, so the same crystal accuracy requirement from
as well.
A.17
Protection diode D2 should be rated for 5 V
Protection diode D2 has the wrong value. It is meant to conduct current, if a voltage too large is connected
to the IDK. This current surge should blow the fuse before ICs are damaged. The current part SMCJ26CA
is rated for 26 V. It should be replaced with SMCJ5.0A that is rated to protect a 5-V input power supply
circuit.
A.18
PHY address LSB for U9 and U15 can be latched incorrectly
The PHY address LSB for U9 and U15 gets determined by the signal level at the PHY's COL pin during
reset release. The PHY has a pull-down resistor connected to this pin to enable latching the value of 0.
Unfortunately, this pin is also connected to one of the RJ-45 connector LEDs that pulls the signal to an
undefined voltage of about 1.4V during the reset time. Therefore, the PHY address can incorrectly latch a
value of 1. The LED circuit should be configured for active-high indication and the connections to the LED
reversed with the cathode connected to ground. This allows the LSB of the address to be properly latched.
Please refer to Section 6 of the
information. The current software workaround programs the RXLINK pin with a pull-down resistor and then
pulses the PHY reset from a GPIO, to cause it to latch the PHY address correctly.
A.19
3.3-V clamp circuit needs more margin
The 3.3-V clamp circuit is tuned too close such that if the 1.8-V supply is 5% low and the 3.3-V supply is
5% high, the clamp will begin conducting. Replacing R897 with a 24.3-KΩ resistor provides the proper
tolerance, so the circuit starts conducting at a delta voltage of 1.75 V rather than the current setting of 1.5
V.
40
Known Deficiencies in AM572x IDK EVM
AM572x Sitara Processors Silicon Revision 2.0 Data Manual (SPRS982)
(SPRS982). The companion PMIC, TPS6590377, was enhanced to provide a
for more information. Also note that these clock generators are used to drive the
TLK1XX Design and Layout Guide Application Report (SLVA531)
Copyright © 2017–2019, Texas Instruments Incorporated
AM572x Sitara Processors Silicon
Section A.15
applies to these crystals
SPRUI64E – May 2017 – Revised September 2019
Submit Documentation Feedback
www.ti.com
that
for more
Advertisement
Table of Contents
