Compaq Armada e500 Series Reference Manual page 48

The specific issues addressed by the PCI Bus Interface Specification for
PCI-to-CardBus bridges for D3 wake-up are:
Preservation of device context: The PCI Power Management Specification version
1.0 states that PRST* must be asserted when transitioning from D3
method to preserve wake-up context must be implemented so that PRST* does not
clear the PME* context registers.
Power source in D3
cold
The PCI1225 addresses these D3 wake-up issues as follows:
Preservation of device context: When PRST* is asserted, bits required to preserve
PME* context are not cleared. To clear all bits in the PCI1225, another reset pin is
defined: G_RST* (global reset). G_RST* is normally only asserted during the initial
power-on sequence. After the initial boot, PRST should be asserted so that PME
context is retained for D3-to-D0 transitions. Bits cleared by G_RST*, but not cleared
by PRST* (if the PME* enable bit is set), are referred to as PME* context bits.
Power source in D3
cold
removed in D3 , an auxiliary power source must be switched to the PCI1225 V
cold
pins. This switch should be a make before break type of switch, so that V
PCI1225 is not interrupted.
PME* context bit means that the bit is cleared only by the assertion of G_RST* when
the PME* enable bit is set (PCI offset A4h, bit 8). If PME* is not enabled, these bits are
cleared when either PRST* or G_RST* is asserted.
Global reset-only bits, as the name implies, are only cleared by G_RST*. These bits are
never cleared by PRST*, regardless of the setting of the PME* enable bit (PCI offset
A4h, bit 8). The G_RST* signal is gated only by the SUSPEND* signal. This means
that assertion of SUSPEND* blocks the G_RST* signal internally, thereby preserving
all register contents.
The SUSPEND* signal, provided for backward compatibility, gates the PRST* (PCI
reset) signal and the G_RST* (global reset) signal from the PCI1225. Besides gating
PRST* and G_RST*, SUSPEND* also gates PCLK inside the PCI1225 to minimize
power consumption.
Gating PCLK does not create any issues with respect to the power switch interface in
the PCI1225. This is because the PCI1225 does not depend on the PCI clock to clock
the power switch interface.
if wake-up support is required from this state.
if wake-up support is required from this state. Because V
to D0. A
cold
is
CC
CC
to the
CC