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U1
Receive
R
1
data
RE
2
0V
DE
3
0V
D
4
Figure 10
illustrates the EVM configurations and the measurement set-up. The right evaluation module
(EVM2) is configured as the driver. Both, driver and receiver enable inputs, DE and RE, receive high
potential through the wire-bridges to VCC at JMP3 and JMP2. Note that EVM2 is turned by 180°.
EVM1 on the left is configured as the receiver. Here, the driver and receiver enable inputs receive low
potential through the wire-bridges to GND at JMP3 and JMP2.
Scope
Ch4
Ch3
Ch2
Ch1
JMP2
1
VCC
JMP11
2
1
/RE
R
3
2
4
3
JMP3
1
VCC
2
DE
B
3
A
4
HVD96
EVM1
Figure 10. EVM Configurations: Left as Receiver EVM, Right as Transmitter EVM
The input data signal entering EVM2 at JMP4 is measured on scope channel 1, probing the signal at
the D-input pin of JMP14. The cross-wiring of the bus wires occurs at the EVM interlink, between the
two TB2 terminal blocks. To proof wire-fault robustness, the differential receiver input and the
single-ended receiver output signals are measured after the cross-wiring. Channels 2 and 3 measure
the bus voltages, V
JMP11. Note that both 5 V power supplies, PSU1 and PSU2 have their ground terminals connected to
the ground and Earth terminals of their respective EVMs.
The scope pictures for the individual examples are shown in
Figure 14
and
Figure 15
SLLU128A – June 2010 – Revised August 2010
DUT_VCC
8
Vcc
R8
B
B
7
0 W
R5
V
OD
A
6
120 W
R9
GND
5
A
0 W
Figure 9. Wire-fault Simulation Using two EVMs
PSU1
5V
TB1
TB2
JMP6
1
1
2
2
B
3
3
A
4
PSU2
5V
and V
, at pin 2 and pin 3 of JMP6, while the receiver output is taken from pin 1 at
A
B
show the top and bottom view of the SN65HVD96 EVM.
Copyright © 2010, Texas Instruments Incorporated
Powering up the EVM and Taking Measurements
DUT_VCC
Vcc
R8
B
B
0 W
R5
A
120 W
R9
GND
A
0 W
D
TB2
3
A
HVD96
2
B
EVM2
1
TB1
Figure
11,
Figure
U1
R
8
1
RE
7
2
5V
DE
6
3
5V
D
Transmit
5
4
data
Signal
Generator
5V
JMP14
JMP4
3
4
2
3
1
2
1
VCC
JMP3
4
3
2
DE
1
VCC
JMP2
4
3
2
/RE
1
VCC
12, and
Figure
13.
Sympol™ Transceiver
7
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