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CDCLVP111-SP EVM Description
(C) This configuration provides a 1 V peak-to-peak differential clock with appropriate offset relative to
earth ground (LVPECL termination point).
(D) Connect 1 or more output pairs to a 50-Ω terminated oscilloscope.
(E) Connect signal generator to CLK0 and nCLK0.
(F) Ensure that J1 is open or set between pins 1 and 2. This enables CLK0. Jumper pins 2 and 3 for CLK1
pair.
(G) Enable power supply 1 and 2.
(H) Enable signal generator outputs.
(I) View outputs on oscilloscope screen.
3
CDCLVP111-SP EVM Description
The following sub-sections describe the CDCLVP111-SP EVM in detail.
3.1
CDCLVP111-SP Clock Mux Selection
The EVM provides a three-pin jumper, J1, to select CLK0 or CLK1 pairs.
Reference
Designator
J1
The CDCLVP111-SP CLK_SEL pin contains a 75-kΩ pulldown to VEE. Leaving J1 without jumper will
select the CLK0 pair, the same as if J1 has pins 1 and 2 shorted. Shorting J1 pins 2 and 3 will select
CLK1 input pair.
3.2
CDCLVP111-SP EVM Input Biasing
The CDCLVP111-SP EVM was designed to allow implementation of flexible input biasing. By default, the
board is configured with two 50-Ω resistors to LVPECL bias level (VCC-2 V, earth ground) for both CLK
inputs. This configuration allows for direct use of LVPECL drivers. The termination resistors R1, R2, R4,
and R5 are placed on the bottom side of the board in a fly-by configuration.
4
CDCLVP111-SP Evaluation Module (CDCLVP111EVM-CVAL)
Table 2. CDCLVP111-SP Jumper Configuration
# of Pins
Default Config
3
Short pins 1-2
Copyright © 2016, Texas Instruments Incorporated
Pin 1 Silkscreen
Pin 2 Silkscreen
VEE
CLK_SEL
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Pin 3 Silkscreen
VCC
SCAU055 – November 2016
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