Toshiba SD-2550A Service Manual page 85

Table 3-5-5 ZR36732 (2/5)
Pin
Name
No.
36 HRDY Host ready output (active: high). When
transmitting a stream through host bus with
this signal, use the signal. And an external
pull up resistor is required.
Confirm the signal becomes active before
transmitting every packet signal, 1 packet
signal is CodBurstLen byte length
transmission signal. After that, it is
available to write the bit stream signals up
to the CodBurstLen byte to the device
continuously.
37 HIRQ# Interrupt request (active: low). Deasserted
by host reading the interrupt status resistor
of the device. And also deasserted either
after host masks the interruption with the
interrupt mask resistor of the device or
after reset.
When HIRQ# is not asserted, 3-state
status starts. (External pull up resistor is
required.)
39 HACK# Host aknowledge output (active: Low).
When the type A protocol is used, the
device asserts the output and informs the
completion of read/write cycle.
When the signal is not active, 3-state
status starts. (External pull up resistor is
required.)
When the type B protocol is used, the
signal works as a Wait output signal. When
using a host with high speed
(microprocessor), the signal connection is
not always required.
GPI/O signal (3 pins)
134 GPIO General bidirectional pin to watch/control
by ADP micro code. After reset, the pin is
defined to use for input. By the ADP
command, setting is available.
145 GPSI General input to be watched by DVP micro
code.
143 GPSO General output to be controlled by DVP
micro code. After reset, the pin develops
Low.
PLL signal (5 pins)
120 GCLK 27.000 MHz clock or X'tal input for main
processor.
117 GCLK1 27.000 MHz master clock input for audio.
In standard use, the pin should be
connected to GCLK.
119 XO Output to X'tal connected to GCLK. When
not using X'tal for GCLK, XO is kept
unconnected.
118 PLLCFG PLL configuration input. During reset,
115 [1:0] modification will be available. For general
use, both pins should be connected to
GNDP.
Analog video port (7 pins)
102 CVBS/G/Y At CVBS, the composite video signal is
(DAC A) developed.
At RGB, G signal is developed.
At YUV, Y signal is developed.
105 Y/R/V At CVBS, Y signal is developed.
(DAC B) At RGB, R signal is developed.
At YUV, V signal is developed.
106 C/B/U At CVBS, C signal is developed.
(DAC C) At RGB, B signal is developed.
At YUV, U signal is developed.
103 CVBS/C Develops either of CVBS or C signal.
(DAC D)
108 RSET Insert a resistor load for DAC gain
adjustment between GND and DAC.
Function
3-26
Table 3-5-5 ZR36732 (3/5)
Pin
Name
No.
111 VREF Apply reference voltage for DAC gain
adjustment.
100 COSYNC Composite sync output. Only when RGB
analog output is selected, the pin takes
effective. For other case, the pin is fixed to
Low.
Digital video port (5 pins)
127 VCLKx2 Main video clock input or output. 27.000
MHz.
92 VCLK Two-divided VCLKx2 signal. The signal is
used as data and sync signal qualifier.
95 HSYNC Horizontal sync bidirectional signal pin. The
polarity and length are programmable.
93 VSYNC Vertical sync bidirectional signal pin. The
polarity and length are programmable.
96 FI Field identification bidirectional signal pin.
The polarity is programmable.
Digital audio port (8 pins)
131 AMCLK Audio master clock input/output. The
sampling frequency can be selected
among 384fs, 256fs, 192fs and 128fs.
(programmable)
133 S/PDIF S/PDIF transmitter output. Available to
(AOUT[3]) connect to DAC as the 4th audio output
(AOUT[3]). After reset, the pin develops
low level signal.
136 AOUT[2:0] PCM stereo audio serial output for DAC.
| After reset, the pin develops low level
138 signal.
113 AIN PCM stereo audio serial input for ADC.
139 ALRCLK AOUT [4:0] and LR clock output of AIN.
The square waveform appears in the
sampling frequency.
The polarity of LR is programmable.
141 ABCLK AOUT [4:0] and bit clock output of AIN.
AOUT is developed at the rising and falling
edges of the clock signal and AIN is
latched.
DVD-DSP interface (13 pins)
151 DVDREQ DVD-DSP data request output (polarity
programmable).
149 DVDVALID DVD-DSP data effective input (polarity
programmable).
148 DVDSOS DVD-DSP data sector start input (polarity
programmable).
152 DVDDAT DVD-DSP data input bus.
| [7:0]
159
150 DVDSTRB DVD-DSP data bit strobe (clock) input.
Polarity programmable.
147 DVDERR DVD-DSP error input. Polarity
programmable.
Function