Toshiba SD-2550A Service Manual page 82

Table 3-5-4 TMP94C251AF(Z) (1/5)
Pin
Name
No.
70 P00~P07 Port 0: I/O port
| D0~D7 Data 0~7: data bus 0~7
77 Initialized to this function in the external
ROM type, TMP94C251A.
Becomes high impedance when not
accessing to the external memory.
79 P10~P17 Port 1: I/O port
| D8~D15 Data 8~15: data bus 8~15
86 Initialized to this function when starting with
data bus width higher than 16 bit in the
external ROM type, TMP94C251A.
Becomes to high impedance when not
accessing to the external memory.
108 P40~P47 Port 4: I/O port
| A0~A7 Address 0~7: address bus 0~7
115 Initialized to this function in the external
ROM type, TMP94C251A.
The signal does not change when not
accessing to the external memory.
99 P50~P57 Port 5: I/O port
| A8~A15 Address 8~15: address bus 8~15
106 Initialized to this function in the external
ROM type, TMP94C251A.
The signal does not change when not
accessing to the external memory.
90 P60~P67 Port 6: I/O port
| A16~A23 Address 16~23: address bus 16~23
97 Initialized to this function in the external
ROM type, TMP94C251A.
The signal does not change when not
accessing to the external memory.
68 P70 Port 70: Output port (initialized to "1"
RD output)
Read: Strobe signal, which reads the
external memory.
Develops no strobe signal when not
accessing to the external memory.
Initialized to this function in the external
ROM type, TMP94C251A.
67 P71 Port 71: Output port (initialized to "1"
WRL output)
Write: Strobe signal, which writes D0 ~ D7
of the external memory.
Develops no strobe signal when not
accessing to the external memory.
66 P72 Port 72: Output port (initialized to "1"
WRH output)
Write: Strobe signal, which writes D8 ~ D15
of the external memory.
Develops no strobe signal when not
accessing to the external memory.
65 P73 Port 73: Output port (initialized to "1"
output)
64 P74 Port 74: Output port (initialized to "1"
output)
63 P75 Port 75: I/O port
BUSRQ Bus request: Signal, which requests to set
the memory interface terminal to high
impedance.
The following terminals become high
impedance. But the state does not change
while functioning as port.
A0~A23, D0~D15, RD, WRLL, WRLH,
CS0~CS5, OE0~OE1, WE0~WE1, RAS
group, CAS group
62 P76 Port 76: Output port (initialized to "1"
BUSAK output)
Bus Acknowledge: Signal, which indicates
that BUSRQ request is received.
60 P80 Port 80: Output port (initialized to "1"
CS0 output)
Chip select 0: Develops "L" level when the
address is within the assigned address
area.
Function
3-23
Table 3-5-4 TMP94C251AF(Z) (2/5)
Pin
Name
No.
59 P81 Port 81: Output (initialized to "1" output)
CS1 Chip select 1: Develops "L" level when the
address is within the assigned address
area.
RAS0 Low address strobe 0: Develops RAS
strobe signal for DRAM when the address
is within the assigned address area.
58 P82 Port 82: Output port (initialized to "1"
CS2 output)
Chip select 2: Develops "L" level when the
address is within the assigned address
area.
57 P83 Port 83: Output port (initialized to "1"
CS3 output)
Chip select 3: Develops "L" level when the
address is within the assigned address
area.
RAS1 Low address strobe 1: Develops RAS
strobe signal for DRAM when the address
is within the assigned address area.
56 P84 Port 84: Output port (initialized to "1"
CS4 output)
Chip select 4: Develops "L" level when the
address is within the assigned address
area.
55 P85 Port 85: Output port (initialized to "1"
CS5 output)
Chip select 5: Develops "L" level when the
address is within the assigned address
area.
29 P86 Port 86: I/O port
WAIT Wait: Bus wait request signal
49 PA0 Port A0: Output port (initialized to "1"
CAS0 output)
Column address strobe 0: Develops CAS
strobe signal for DRAM when the address
is within the assigned address area.
LCAS0 Lower column address strobe 0: Develops
lower CAS strobe signal for DRAM when
the address is within the assigned address
area.
50 PA1 Port A1: Output port (initialized to "1"
UCAS0 output)
Upper column address strobe 0: Develops
upper CAS strobe signal for DRAM when
the address is within the assigned address
area.
51 PA2 Port A2: Output port (initialized to "1"
OE0 output)
Out enable 0: Develops out enable signal
for DRAM.
52 PA3 Port A3: Output port (initialized to "1"
OE1 output)
Out enable 1: Develops out enable signal
for DRAM.
53 PA4 Port A4: Output port (initialized to "1"
WE0 output)
Write enable 0: Develops write enable
signal for DRAM.
44 PB0 Port B0: Output port (initialized to "1"
CAS1 output)
Column address strobe 1: Develops CAS
strobe signal for DRAM when the address
is within the assigned address area.
LCAS1 Lower column address strobe 1: Develops
lower CAS strobe signal for DRAM when
the address is within the assigned address
area.
45 PB1 Port B1: Output port (initialized to "1"
UCAS1 output)
Upper column address strobe 1: Develops
upper CAS strobe signal for DRAM when
the address is within the assigned address
area.
Function