Table 8-112 Supervised Telecom Clocks Reference List; Table 8-111 Telecom Clock 166Hz Control Register - Emerson ATCA-8310 Manual

CPLD and FPGA

Table 8-111 Telecom Clock 166Hz Control Register

Address: 0x61
Bit Description
5:0 Select 0 to 47 phase offset of :
0: No shift
1: 1 x Frame sync period (125 us) shifted
N (2, 3..., 47): N x Frame sync periods (125 us) shifted
48 to 63: Reserved
6 ADM Mode:
0: Normal Backplane. Use internal generated 166 Hz. Drive
ADM_MODE_ high
1: ADM Custom Backplane. Use ADM_CLK_166HZ. Drive
ADM_MODE_ low.
7 Reserved
Telecom Clock Monitor Registers
All incoming telecom clock can be monitored and measured in the range from 100 Hz to 100
MHz. Up to 16 different clock inputs may be monitored. See table below.

Table 8-112 Supervised Telecom Clocks Reference List

Number
0
1
2
3
4
5
6
7
8 - 15
320
Name Description
CLK1A_IN Backplane Input Clock CLK1A_IN
CLK1B_IN Backplane Input Clock CLK1B_IN
CLK2A_IN Backplane Input Clock CLK2A_IN
CLK2B_IN Backplane Input Clock CLK2B_IN
ADM_CLK_166HZ Backplane Input ClockADM_166Hz
CLK_77MHZ_IN Clock 77MHz from ACS8520
CLK_FRSYNC_IN Clock FRSYNC from ACS8520
CLK_T4_IN Clock T4 from ACS8520
- Reserved
Default
PWR_GOOD: 0
PWR_GOOD: 0
0
ATCA-8310 Installation and Use (6806800M72D)
Access
SPP: r/w
SPP: r/w
r