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Name
Mnemonic
INTERLOCK
IL(02)
INTERLOCK
CLEAR
ILC(03)
JUMP
JMP(04)
JUMP END
JME(05)
SHIFT REGISTER
I
SFT(10)
P
R
KEEP
S
KEEP(11)
R
REVERSIBLE
II
COUNTER
CNTR (12)
DI
R
DIFFERENTIATE
UP
DIFU(13)
DIFFERENTIATE
DOWN
DIFD(14)
HIGH-SPEED
TIMER
TIMH(15)
WORD SHIFT
WSFT(16)
Symbol
If an interlock condition is OFF, all outputs
and all timer PVs between the current
IL(02)
IL(02) and the next ILC(03) are turned OFF
or reset, respectively. Other instructions
are treated as NOP. Counter PVs are
ILC(03)
maintained. If the execution condition is
ON, execution continues normally.
When the execution condition for the
JMP(04) instruction is ON, all instructions
JMP(04)
between JMP(04) and the next JME(05)
are ignored or treated as NOP(00)
JME(05)
Creates a bit shift register for data from the
starting word (St) through to the ending
word (E). I: input bit; P: shift pulse; R: reset
SFT(10)
input. St must be less than or equal to E. St
St
and E must be in the same data area.
E
15
Defines a bit (B) as a latch, controlled by
the set (S) and reset (R) inputs.
KEEP(11)
B
Increases or decreases the PV by one
whenever the increment input (II) or
decrement input (DI) signals, respectively,
CNTR(12)
go from OFF to ON. SV: 0 to 9999; R: reset
N
input. Each TC bit can be used for one
SV
timer/counter only. The TC bit is entered as
a constant.
DIFU(13) turns ON the designated bit (B)
for one scan on reception of the leading
DIFU(13)
B
(rising) edge of the input signal; DIFD(14)
turns ON the bit for one scan on reception
of the trailing (falling) edge. A maximum of
DIFD(14)
B
16 DIFFERENTIATE UP/DOWN instruc-
tions can be used
A high-speed, ON-delay (decrementing)
timer. SV: 00.02 to 99.99 s. Each TC bit can
be assigned to only one timer or counter.
TIMH(15) N
The TC bit is entered as a constant.
SV
The data in the words from the starting
word (St) through to the ending word (E), is
shifted left in word units, writing all zeros
WSFT(16)
into the starting word. St must be less than
St
or equal to E, and St and E must be in the
E
same data area.
Function
00
15
00
St
E
Appendix C
Operand Data Areas
None
None
St/E:
IR (except IR00 and IR02)
Work bits (except word 12)
IN
B:
IR (except IR00 and IR02)
Work bits
N:
SV:
TC
IR
SR
Work bits
#
B:
IR (except IR00 and IR02)
Work bits
N:
SV:
TC
IR
SR
Work bits
#
St/E:
IR
Work bits (except word 12)
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