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1
2
A
B
C
F27
3V3_VCC
3V3_ETH_D
220R
C339
D
10u
10V
F28
3V3_VCC
3V3_ETH
220R
C342
10u
10V
E
R208
R203
PHYTXP
47R
47R
49R9
49R9
R204
R202
PHYTXN
47R
47R
49R9
49R9
F
Route both traces of each differential pair
as identical to each other. If possible at 6mil
width/6mil parallel spacing, and at least 18
mils away from all other signals.
1
2
3
TXD1
3V3_ETH_D
3V3_ETH_D
3V3_ETH
10k
R85
nETH_RESET
PHYRXP
PHYRXN
3V3_ETH
F11
330R
3
4
5
R81
3V3_ETH_D
10k
25
TXD1
22R
R322
26
TXD2
27
TXD3
R297
4k7
R241
28
COL
1k
/CONFIG0
R300
4k7
29
KSZ8041NL
CRS
R299
/CONFIG1
4k7
30
LED0
31
LED1
32
RST#
S7
C341
10u
10V
Internal 1.8 V
Generation
Route this area void of all
PWR/GND planes and high
speed nets, except for the
chassis ground.
Also keep traces short and
route as matched length
differential pairs. Do not place
any parts or traces under the
transformer.
TR1
PHYRXP
1
16
TX+
R512
2
15
75R
4
13
PHYRXN
3
14
TX-
5
12
PHYTXP
6
11
RX+
R508
7
10
75R
PHYTXN
8
9
RX-
4
5
6
R302
4k7
3V3_ETH_D
16
RXD0
15
RXD1
14
RXD2
13
RXD3
U10
12
MDC
11
MDIO
10
REXT
9
XI
30040168 25Mhz
X3
S6
OPTIONAL 25MHZ REFERENCE CLOCK XTAL FOR KSZ8041RNL
TX+
1
TX+
TX-
2
TX-
RX+
3
RX+
4
GND1
R525
5
75R
GND2
RX-
6
RX-
7
GND3
R529
8
GND4
75R
6
7
8
RXD0
R337
22R
RXD1
R336
22R
3V3_ETH_D
MDC
MDIO
100p
50V
C63
R530
6k8
6K49
TXCLK
R440
33R
PROJECT NAME :
A3
17mb38-1
19
19
SCH NAME :
ETHERNET
SHEET:
OF:
DRAWN BY :
29-01-2010_15:15
7
8
A
B
C
D
E
F
A X M
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