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57
58
60
59
62
63
61
56
84
86
85
4
5
23
6
64
┆
71
83
┆
76
MISC port control signal
162
163
157
158
159
205
204
SDRM 控制端口
124
┆
121
118
┆
113
125
126
156
133
109
87
128
SCL
SDA
GPIO0
GPIO1
WR#
RD#
CS
INTN
ALE
RESET
V5SF
DP_HS
DP_VS
DP_CLK
DP_DE_FLD
ADDR0
┆
ADDR7
A_D0
┆
A_D7
CVBS_OUT2
CVBS_OUT1
TEST MODE
AIN_HS
AIN_VS
XTALI
XTALO
MA0
┆
MA3
MA4
┆
MA9
MA10
MA11
DQM0
DQM1
DQM2
DQM3
BA0
IIC bus（clock）
IIC bus（data）
GPIO1 selection signal
GPIO2 selection signal
CPU write signal
CPU read signal
CPU chip selection signal（low level effective）
Interrupt signal（low level effective）
Address latch signal
Reset signal (high level effective)
SF Power（+5V）
Line synchronization signal
Field synchronization signal
Clock signal
DE I/O terminal
CPU address（R0~R7）signal
CPU address/data passage
SCART2 interface CVBS signal output
SCART1 interface CVBS signal output
Test mode signal (grounding)
Line synchronization signal
Field synchronization signal
Crystal oscillator interface
Memory address （A0~A11）
Memory read/write byte signal
Memory stack address selection
9
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