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The SWAP_COMM_MODE() subcommand immediately changes the communications interface to that
selected by the Comm Type configuration, while the SWAP_TO_HDQ() subcommand immediately
changes the interface to HDQ using the ALERT pin.
With HDQ, the least significant bit (LSB) of a data byte (command) or word (data) is transmitted first.
The 8-bit command code consists of two fields: the 7-bit HDQ command code (bits 0–6) and the 1-bit R/W field
(MSB Bit 7). The R/W field directs the device to do one of the following:
•
Accept the next 8 bits as data from the host to the device or
•
Output 8 bits of data from the device to the host in response to the 7-bit command.
The HDQ peripheral on the BQ76952 device can transmit and receive data as an HDQ responder only.
The return-to-one data bit frame of HDQ consists of the following sections:
1. The first section is used to start the transmission by the host sending a Break (the host drives the HDQ
interface to a logic-low state for a time t
interface for a time t
(BR)
2. The next section is for host command transmission, where the host transmits 8 bits by driving the HDQ
interface for 8 T
(CYCH)
writing a "0") or T
(HW1)
T
time slot.
(CYCH)
3. The next section is for data transmission where the host (if a write was initiated) or device (if a read was
initiated) transmits 8 bits by driving the HDQ interface for 8 T
is driving) time slots. The HDQ line is driven low for a time T
"1"), T
(device writing a "0"), or T
(DW0)
high to complete the time slot. The HDQ interface does not auto-increment, so a separate transaction must
be sent for each byte to be transferred.
15 Cell Balancing
15.1 Cell Balancing Overview
The BQ76952 device supports passive cell balancing by bypassing the current of a selected cell during charging
or at rest, using either integrated bypass switches between cells, or external bypass FET switches. The device
incorporates a voltage-based balancing algorithm which can optionally balance cells autonomously without
requiring any interaction with a host processor. Or if preferred, balancing can be entirely controlled manually
from a host processor. For autonomous balancing, the device will only balance non-adjacent cells in use (it
does not consider inputs used to measure interconnect as cells in use). To avoid excessive power dissipation
within the BQ76952 device, the maximum number of cells allowed to balance simultaneously can be limited
by configuration setting. For host-controlled balancing, adjacent as well as non-adjacent cells can be balanced.
Host-controlled balancing can be controlled using specific subcommands sent by the host. The device also
returns status information regarding how long cells have been balanced through subcommands.
When host-controlled balancing is initiated using subcommands, the device starts a timer and will continue
balancing until the timer reaches a programmed value, or a new balancing subcommand is issued (which resets
the timer). This is included as a precaution, in case the host processor initiated balancing but then stopped
communication with the BQ76952 device, so that balancing would not continue indefinitely.
The BQ76952 device can automatically balance cells using a voltage-based algorithm based on environmental
and system conditions. Several settings are provided to control when balancing is allowed, which are described
in detail in the
BQ76952 Technical Reference
Due to the current that flows into the cell input pins on the BQ76952 device while balancing is active, the
measurement of cell voltages and evaluation of cell voltage protections by the device is modified during
balancing. Balancing is temporarily disabled during the regular measurement loop while the actively balanced
cell is being measured by the ADC, as well as when the cells immediately adjacent to the active cell are being
measured. Similarly, balancing on the top cell is disabled while the stack voltage measurement is underway.
Copyright © 2021 Texas Instruments Incorporated
) followed by a Break Recovery (the host releases the HDQ
(B)
).
time slots. For each time slot, the HDQ line is driven low for a time T
(host writing a "1"). The HDQ pin is then released and remains high to complete each
(device writing a "1"). The HDQ pin is then released and remains
(DW1)
Manual.
Product Folder Links:
SLUSE13A – JANUARY 2020 – REVISED MAY 2021
Note
(if host is driving) or T
(CYCH)
(host writing a "0"), T
(HW0)
BQ76952
BQ76952
(host
(HW0)
(if device
(CYCD)
(host writing a
(HW1)
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