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< 2- MT6572_POWER > Rev_0.1
Vproc remote sense :
differential 4mil with good shielding,
from the BB to PMIC
GND_VPROC_FB
VPROC_FB
+1V2_MTK_LPDDR2
LGE Internal Use Only
<2-3-2-1-3_MT6572M_POWER>
0
R2300
R2301
0
4mil - differential - GND shielding
120mil
+1V15_MTK_PROC
Size is changed ( 12/26 )
C2300
C2301
C2302
C2303
C2304
C2305
C2306
C2307
C2308
C2309
10u
10u
10u
4.7u
2.2u
2.2u
1u
1u
1u
1u
124
120
121 122
123
C2322
C2323
0.1u
0.1u
If double-sided SMT, put below BB.
If single-sided SMT, put around Memory.
Rev_0.3
VCCK_CPU_1
P6
K6
P7
VCCK_1
VCCK_CPU_2
K7
VCCK_2
VCCK_CPU_3
P8
K8
VCCK_3
VCCK_CPU_4
P9
K9
VCCK_4
VCCK_CPU_5
R6
K11
VCCK_5
VCCK_CPU_6
R7
K12
R8
VCCK_6
VCCK_CPU_7
K14
VCCK_7
VCCK_CPU_8
R9
K15
VCCK_8
VCCK_CPU_9
T6
K16
VCCK_9
VCCK_CPU_10
T7
K17
VCCK_10
VCCK_CPU_11
T8
L6
T9
VCCK_11
VCCK_CPU_12
L7
U6
VCCK_12
VCCK_CPU_13
L8
VCCK_13
VCCK_CPU_14
U7
L9
VCCK_14
L17
VCCK_15
DVDD18_MIPIRX
T25
M6
VCCK_16
DVSS18_MIPIRX
U25
M7
VCCK_17
M8
VCCK_18
DVDD18_MIPITX
R25
M9
VCCK_19
DVSS18_MIPITX
P25
M10
VCCK_20
M17
VCCK_21
AVDD18_USB
H23
R17
G24
VCCK_22
U2100
AVDD33_USB
J8
VCCK_23
AVSS33_USB
G23
J9
VCCK_24
MT6572M
J10
VCCK_25
AVDD28_DAC
F1
J11
VCCK_26
AVDD18_AP
E5
J14
U9
VCCK_27
DVDD18_PLLGP
J15
VCCK_28
J16
VCCK_29
AVDD18_MD
D3
T16
VCCK_30
AVSS18_MD_1
A1
T17
VCCK_31
AVSS18_MD_2
A4
J17
VCCK_32
AVSS18_MD_3
C3
U12
E2
VCCK_33
AVSS18_MD_4
103
103
U13
VCCK_34
U14
VCCK_35
AVDD18_WBG
F18
U15
VCCK_36
U16
VCCK_37
DVDD18_MC0
AA1
U17
K20
VCCK_38
DVDD18_CAM
DVDD18_VIO_1
L3
W9
VCCIO_EMI_1
DVDD18_VIO_2
J19
W12
VCCIO_EMI_2
DVDD18_VIO_3
H13
R2303
0
W14
VCCIO_EMI_3
DVDD18_LCD
AB24
W16
VCCIO_EMI_4
W19
VCCIO_EMI_5
DVDD3_LCD
W24
DVDD3_MC1
K24
DVDD28_BPI
C10
C2324
C2325
C2326
C2327
0.1u
DNI
1u
1u
Close to BB IC,
recommand < 150mil
for eMMC
Based on your system level design, if better FM performance is needed on your system,
please refer to FM desense performance enhance proposal.
- 134 -
6. CIRCUIT DIAGRAM
+1V8_MTK_VIO
+1V8_MTK_VIO
+3V3_MTK_VUSB
+2V8_MTK_VTCXO
Based on your system level design
+1V8_MTK_VIO
Note 3
+1V8_MTK_VIO
1. use RTP (Resistive Touch Panel)
Note 1
Cap close to BB IC
+1V8_MTK_VIO
AVDD18_AP = ext. 1.8V LDO
Dedicate VSS ball, must return to cap then to main GND
2. use AUXADC, no RTP
DVSS18_MIPIRX(U25) --> C2321
AVDD18_AP = VIO18
DVSS18_MIPITX(P25) --> C2320
Size is changed ( 12/26 )
3. no use AUXADC, no RTP
Note 2
R2302
0
+1V8_MTK_VCN
AVDD18_AP = VIO18
(i.e : DO NOT use VIO18 when touch is RTP)
+1V8_MTK_VIO
+3V3_MTK_VMC
83 83
+2V8_MTK_VIO
C2328
C2329
0.1u
0.1u
Note 2
Close to MT6572
Copyright © 2014 LG Electronics. Inc. All right reserved.
Only for training and service purposes
cap = 0.1 uF
cap = 0.1 uF (NC)
cap = none (share with C2314)
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