LG 55G2 Service Manual page 50

FRC_VDDC10 +1.5V_FRC_DDR
+1.26V_FRC FRC_VDDC10
L9602
BLM18SG121TN1D
C9611 C9613 C9619 C9623 C9626 C9628
C9600
0.1uF
0.1uF 22uF 22uF 0.22uF 0.1uF 0.1uF
10V 10V 6.3V
+1.26V_FRC DVDD_DDR_1V
L9600
BLM18SG121TN1D
C9601 C9608 C9612
0.1uF 22uF 0.1uF
10V
Place Close to Bead
+3.3V_FRC FRC_VDD33 FRC_VDD33 (VDDP)
L9601
BLM18SG121TN1D
C9602 C9606 C9615 C9620 C9624
0.1uF 0.1uF 0.1uF 0.1uF 0.22uF
6.3V
AFRC_VDD33
+3.3V_FRC AFRC_VDD33
L9603
BLM18SG121TN1D
C9603 C9607 C9616 C9621
0.1uF 0.1uF
0.1uF 0.1uF
+3.3V_FRC FRC_AVDD_PLL FRC_AVDD_PLL
L9604
BLM18SG121TN1D
C9604 C9609 C9614 C9618
0.1uF 0.1uF 10uF 0.1uF
6.3V
FRC_AVDD_LVDS33
+3.3V_FRC FRC_AVDD_LVDS33
L9605
BLM18SG121TN1D
C9605 C9610 C9617 C9622 C9625 C9627
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
GPIO1 : HI => B8/94, LOW => B4/98
CHIP_CONF : {GPIO8, PWM1, PWM0}
CHIP_CONF = 3'd5 : boot from interal SRAM
CHIP_CONF = 3'd6 : boot from EEPROM
CHIP_CONF = 3'd7 : boot from SPI Flash
URSA5 CONFIGURATION
+3.3V_FRC
PWM0_CONFIG
PWM1_CONFIG
GPIO[8]
GPIO[1]
URSA5 H/W OPTION
+3.3V_FRC
URSA_MODEL_OPT_0
URSA_MODEL_OPT_1
URSA_MODEL_OPT_2
URSA_MODEL_OPT_3
MODEL OPTION
PIN NAME PIN NO.
MODEL_OPT_0 D10
MODEL_OPT_1 D11
D12
MODEL_OPT_2
D13
MODEL_OPT_3
Debugging for URSA5
P9600
12507WR-04L
URSA5_DEBUG
1
2
I2C_SCL1
URSA5_DEBUG
R9618
R9601 22
3 0
SCL2_+3.3V_DB
URSA5_MP
SCL2_+3.3V_URSA
URSA5_DEBUG
R9619
R9600 22 0
4
SDA2_+3.3V_DB
OPT
SCL2_+3.3V_DB
5
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes
+1.5V_FRC_DDR
C9629 C9630 C9631 C9632 C9633
0.22uF 0.1uF 0.1uF 0.1uF 1uF
6.3V 6.3V
FRC_A[0-13]
FRC_A[0] P14
DDR3_A0/DDR2_NC
FRC_A[1] G15
DDR3_A1/DDR2_A8
FRC_A[2] N14
DDR3_A2/DDR2_NC
FRC_A[3] L15
DDR3_A3/DDR2_A10
FRC_A[4] H15
DDR3_A4/DDR2_A2
FRC_A[5] L14
DDR3_A5/DDR2_A3
FRC_A[6] G14
DDR3_A6/DDR2_A4
FRC_A[7] N12
DDR3_A7/DDR2_A5
FRC_A[8] G13
DDR3_A8/DDR2_A6
FRC_A[9] N13
DDR3_A9/DDR2_A9
FRC_A[10] H14
DDR3_A10/DDR2_RASZ
FRC_A[11] F15
DDR3_A11/DDR2_A11
FRC_A[12] H13
DDR3_A12/DDR2_A0
FRC_A[13] P13
DDR3_A13/DDR2_A12
M12
FRC_BA0 DDR3_BA0/DDR2_BA2
H12
FRC_BA1
DDR3_BA1/DDR2_CASZ
L13
FRC_BA2 DDR3_BA2/DDR2_A1
F16
FRC_MCLK DDR3_MCLK/DDR2_MCLK
F17
FRC_MCLKB
DDR3_MCLKZ/DDR2_MCLKZ
J13
FRC_CKE DDR3_CKE/DDR2_ODT
K12
FRC_ODT DDR3_ODT/DDR2_CKE
L12
FRC_RASB
DDR3_RASZDDR2_WEZ
K13
FRC_CASB DDR3_CASZ/DDR2_BA1
K14
FRC_WEB DDR3_WEZ/DDR2_BA0
M14
FRC_DDR3_RESETB DDR3_RESET/DDR2_A7
N16
FRC_DQSL DDR3_DQSL/DDR2_DQSL
M17
FRC_DQSU
DDR3_DQSU/DDR2_DQSU
M16
FRC_DQSLB
DDR3_DQSBL/DDR2_DQSBL
M15
FRC_DQSUB DDR3_DQSBU/DDR2_DQSBU
J15
FRC_DML DDR3_DQML/DDR2_DQU5
R16
FRC_DQL[0-7]
FRC_DMU DDR3_DQMU/DDR2_DQU4
FRC_DQL[0] R17
DDR3_DQL0/DDR2_DQU3
FRC_DQL[1] H17
DDR3_DQL1/DDR2_DQL0
FRC_DQL[2] R15
DDR3_DQL2/DDR2_DQL6
FRC_DQL[3] J17
DDR3_DQL3/DDR2_DQL7
FRC_DQL[4] T17
DDR3_DQL4/DDR2_DQL3
FRC_DQL[5] H16
DDR3_DQL5/DDR2_DQL2
FRC_DQL[6] T15
DDR3_DQL6/DDR2_DQL1
FRC_DQL[7] G16
DDR3_DQL7/DDR2_DQL5
FRC_DQU[0] K15
DDR3_DQU0/DDR2_DQU7
FRC_DQU[1] N15
DDR3_DQU1/DDR2_DQML
FRC_DQU[2] K17
DDR3_DQU2/DDR2_DQU2
FRC_DQU[3] P17
DDR3_DQU3/DDR2_DQU6
FRC_DQU[4] L17
DDR3_DQU4/DDR2_NC
FRC_DQU[5] P16
DDR3_DQU5/DDR2_DQU1
FRC_DQU[6] K16
DDR3_DQU6/DDR2_DQU0
FRC_DQU[7] P15
DDR3_DQU7/DDR2_DQMU
F14
FRC_DQU[0-7]
DDR3_NC/DDR2_A13
T16
DDR3_NC/DDR2_DQL4
D14
I2CM_SCL
D15
I2CM_SDA
33 R9622 P1
I2CS_SCL
SCL2_+3.3V_URSA
P2
33 R9623
SDA2_+3.3V_URSA I2CS_SDA
HIGH LOW
L/DIM_10BLOCK L/DIM_16BLOCK
RESERVED RESERVED
LVDS_EXT_URSA5 LVDS_S7M_PLUS
RESERVED RESERVED
SW9600
JS2235S
1 6
I2C_SDA1
R9620
0
URSA5_MP
2 5
SDA2_+3.3V_URSA
URSA5_DEBUG R9621
0
OPT
3 4
SDA2_+3.3V_DB
PLACE TERMINATION RESISTORS CLOSE TO URSA5
R9624 R9631
100 100
R9625 R9632
100 100
R9626 R9633
100 100
R9627 R9634
1M
100 100
R9639
R9628 R9635
100 100
R9629 R9636
100 100
IC9600
LGE7303C
+3.3V_FRC
R9630
10K
R9637 33
FRC_RESET
[SPI FLASH(2Mbit)]
+3.3V_FRC
IC9601
R9648 R9650 W25X20BVSNIG
4.7K 10K
CS VCC
1 8
SPI_CS
R9649 DO HOLD R9653
2 7
SPI_DO
33 3.3K
WP CLK
3 6
SPI_SCLK
GND DIO
4 5
SPI_DI
URSA5_FLASH_WINBOND_2M
C8
TXA0P/GCLK6/BLUE[7] TXA0P
C9
TXA0N/GCLK5/BLUE[6] TXA0N
B8
TXA1P/OPT_N/LK3/BLUE[9] TXA1P
A8
TXA1N/FLK/BLUE[8] TXA1N
A7
TXA2P/GREEN[1] TXA2P
B7
TXA2N
TXA2N/OPT_P/LK2/GREEN[0]
C6
TXACLKP/RLV0N/GREEN[3] TXACLKP
C7
TXACLKN
TXACLKN/RLV0P/GREEN[2]
B6
TXA3P/RLV1N/GREEN[5] TXA3P
A6
TXA3N
TXA3N/RLV1P/GREEN[4]
A5
TXA4P/RLV2N/GREEN[7] TXA4P
B5
TXA4N
TXA4N/RLV2P/GREEN[6]
C4
TXB0P/RLV3N/GREEN[9] TXB0P
C5
TXB0N/RLV3P/GREEN[8] TXB0N
B4
TXB1P/RLVCLKN/RED[1] TXB1P
A4
TXB1N
TXB1N/RLVCLKP/RED[0]
A3
TXB2P/RLV4P/RED[3]/EPI_A3P TXB2P
B3
TXB2N
TXB2N/RLV4N/RED[2]/EPI_A3N
C2
TXBCLKP/RLV5N/RED[5]/EPI_A2P TXBCLKP
C3
TXBCLKN
TXBCLKN/RLV5P/RED[4]/EPI_A2N
B2
TXB3P/RLV6N/RED[7]/EPI_A1P TXB3P
A2
TXB3N
TXB3N/RLV6P/RED[6]/EPI_A1N/
C1
TXB4P/RLV7N/RED[9]/EPI_A0P TXB4P
B1
TXB4N
TXB4N/RLV7P/RED[8]/EPI_A0N
C16
TXC0P/SOE TXC0P
B17
TXC0N/POL TXC0N
B16
TXC1P/GSP_R TXC1P
A16
TXC1N
TXC1N/GSP/VST
A15
TXC2P/GOE/GCLK1 TXC2P
B15
TXC2N
TXC2N/GSC/GCLK3
C14
TXCCLKP/LLV0N TXCCLKP
C15
TXCCLKN
TXCCLKN/LLV0P
B14
TXC3P/LLV1N TXC3P
A14
TXC3N
TXC3N/LLV1P
A13
TXC4P/LLV2N TXC4P
B13
TXC4N/LLV2P TXC4N
C12
TXD0P/LLV3N TXD0P
C13
TXD0N/LLV3P TXD0N
B12
TXD1P/LLVCLKN TXD1P
A12
TXD1N
TXD1N/LLVCLKP
A11
TXD2P/LLV4N/EPI_B3P TXD2P
B11
TXD2N
TXD2N/LLV4P/EPI_B3N
C10
TXDCLKP/LLV5N/BLUE[1]/EPI_B2P TXDCLKP
C11
TXDCLKN
TXDCLKN/LLV5P/BLUE[0]/EPI_B2N
B10
TXD3P/LLV6N/BLUE[3] TXD3P
A10
TXD3N
TXD3N/LLV6P/BLUE[2]/EPI_B1N
A9
TXD4P/LLV7N/BLUE[5]/EPI_B0P TXD4P
B9
TXD4N/LLV7P/BLUE[4]/EPI_B0N TXD4N
D10
URSA_MODEL_OPT_0
MOD_GPIO0/VDD_ODD/HSYNC
D11
MOD_GPIO1/VDD_EVEN/VSYNC URSA_MODEL_OPT_1
D12
URSA_MODEL_OPT_2
MOD_GPIO2/PWM13/GCLK4/LCK
D13
MOD_GPIO3/PWM14/GCLK2/LDE
URSA_MODEL_OPT_3
U12
R9651 33
PWM0_CONFIG
PWM0/SCAN_BLK1
T12
R9652
33
PWM1/SCAN_BLK2 PWM1_CONFIG
G3
LPLL_FBCLK
E17
LPLL_OUTCLK
H3
LPLL_REFIN
LG1152 A0 2011. 02. 16
URSA5 block 52 55
LGE Internal Use Only