JVC MX-G71R Service Manual page 39

LC72723 (IC3) : RDS demodulation
1. Pin Assignment
VREF
1
MPXIN 2
Vdda
3
Vssa
4
FLOUT 5
CIN
6
TBS
7
XOUT
8
2.Block diagram
VREF VREF
Vdda Vdda
REFERENCE REFERENCE
VOLTAGE VOLTAGE
Vssa Vssa
ANTIALIASING ANTIALIASING
MPXIN MPXIN
FILTER FILTER
TEST TEST
TEST TEST
3. Pin functions
Pin
Symbol I/O
No.
1
O
VREF
MPXIN I
2
Vdda
3
Vssa
4
O
5
FLOUT
6 CIN I
TEST I
7
8 XOUT O
9 I
XIN
Vssd
10
11 Vddd
I
12 MODE
13 I
RST
14 RDDA O
RDCL I/O
15
RDS-ID/READY output (negative polarity)
RDS-ID
16
O
READY
RDS-ID/READY
16
RDCL
15
14 RDDA
RST
13
MODE
12
Vddd
11
Vssd
10
XIN
9
Top View
FLOUT CIN FLOUT CIN
VREF VREF
57kHz 57kHz
BPF BPF
SMOOTHING SMOOTHING
(SCF) (SCF)
FILTER FILTER
CLK(4.332MHz)
CLK(4.332MHz)
OSC
OSC
XIN XIN
XDUT XDUT
Reference voltage output (Vdda/2)
Baseband (multiplexed) signal input
Analog power supply (+5V)
Analog ground
Sub carrier input (filter output)
Subcarrier input (comparator input)
Test input
Crystal oscillator output (4.332MHz)
Crystal oscillator input (external reference input)
Digital ground
Digital power supply
Read mode setting (0:master,1:slave)
RDS-ID/RAM reset (positive polarity)
RDS data output
RDS clock output (master mode)/RDS clock input (slave mode)
CLOCK CLOCK
PLL PLL
RECOVERY RECOVERY
(57kHz) (57kHz)
(1187.5kHz) (1187.5kHz)
DATA DATA
DECODER DECODER
RAM RAM
(128-bits) (128-bits)
RDS-ID RDS-ID
DETECT DETECT
Function
MX-G71R
Vddd Vddd
Vssd Vssd
RDDA RDDA
RDCL RDCL
MDDE MDDE
RST RST
RDS-ID/ RDS-ID/
READY READY
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