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CCDS CARD Information
Release Date
2013.08.17
Based on Reference Schematic
Rev.BA
80-NE925-41 MSM8926 BASEBAND PRELIMINARY REFERENCE SCHEMATIC_BA
VBUS_USB_IN
VBUS_USB_IN
+5V0_VREG_BHARGER
+5V0_VREG_BHARGER
+VPWR
CHG_PGND
VBAT
VBAT_SENSE
VBAT_SENSE_P
Note 2
+VPWR
C4146
If BMS_CSP and BMS_CSN pins are not used,
please connect them to VPH_PWR.
Note 2
1'st : Use internal sensing Resistor
VCOIN
VBAT_SENSE_N
+5V0_VREG_BHARGER
R4140
0
+2V1_VSW_S4
+VPWR
+VPWR
LGE Internal Use Only
< 4-1-3-2_PMIC_PM8926_POWER >
C4131
10n
C4132
100n
L4133
1u
50V
C4145
0.1u
0.47u
+VPWR
R4135
DNI
R4138
DNI
+VPWR
Note 1
+1V35_VSW_S3
GR1 : L1, L2, L4, L5
GR5 : L14, L12
GR2 : L3, L24, L26
GR6 : L15, L16, L17, L18
GR3 : L6, L7, L8, L9, L27
GR4 : L10, L11, L13
GR7 : L19, L20, L21, L22, L23, L28
+2V1_VSW_S4
+2V1_VSW_S4
+VPWR
+2V075_VREG_L25
+VPWR
Note 3
If you don't use bypass Boost, Connect +VPWR
Note 4
GR1 : L1, L2, L4, L5
GR2 : L3, L24, L26
GR3 : L6, L7, L8, L9, L27
GR4 : L10, L11, L13
GR5 : L14, L12
GR6 : L15, L16, L17, L18
GR7 : L19, L20, L21, L22, L23, L28
Note 5
Place input caps close to respective VIN pins.
Each capacitor GND should be star routed to their respective reference ground
(GND_S1, GND_S2, GND_S3, GND_S4)
Then input caps should via directly to main ground
Rev_0.6
L4130
240n
161
8
USB_IN_1
VSW_S1_1
172
21
USB_IN_2
VSW_S1_2
Remote Sense
20
R4132
VREG_S1
0
171
OVP_CP_DRV
L4131
240n
162
45
OVP_OUT
VSW_S2_1
167
46
VDRV_P
VSW_S2_2
58
VSW_S2_3
Remote Sense
56
R4133
0
VREG_S2
143
VCHG_1
155
35
L4132
1u
VCHG_2
VSW_S3
36
VREG_S3
154
VSW_CHG_1
166
81
L4134
2.2u
VSW_CHG_2
VSW_S4
95
VREG_S4
152
VPH_PWR_1
164
80
L4135
1u
VPH_PWR_2
VSW_S5
78
VREG_S5
140
BATFET_CP_DRV
139
VBAT_1
151
VBAT_2
163
15
VBAT_3
VREG_L1
156
3
VBAT_SNS
VREG_L2
2
VREG_L3
131
37
BMS_BYP
VREG_L4
107
25
BMS_CSP
VREG_L5
96
105
BMS_CSN
VREG_L6_1
76
106
VCOIN
VREG_L6_2
116
U4100
VREG_L7
104
118
VDD_FLASH
VREG_L8
4
128
VDD_GR1
VREG_L9
1
PM8926
38
VDD_GR2_1
VREG_L10
11
16
VDD_GR2_2
VREG_L11
115
71
VDD_GR3
VREG_L12
27
14
VDD_GR4
VREG_L13
59
49
VDD_GR5_1
VREG_L14
60
43
VDD_GR5_2
VREG_L15
7
19
VDD_GR6
VREG_L16
41
18
VDD_GR7
VREG_L17_1
48
30
VDD_L25
VREG_L17_2
32
VREG_L18
121
29
AVDD_BYP
VREG_L19
170
55
VPRE_BYP
VREG_L20
9
53
VDD_S1_1
VREG_L21
10
52
VDD_S1_2
VREG_L22
22
51
GND_S1_1
VREG_L23
33
12
GND_S1_2
VREG_L24
34
70
VDD_S2
VREG_L25
57
24
1200mA, Source S3
GND_S2_1
VREG_L26
600mA, Source S4
67
127
GND_S2_2
VREG_L27
68
50
150mA
GND_S2_3
VREG_L28
47
VDD_S3
23
94
GND_S3
VOUT_LVS1
93
VDD_S4
69
138
GND_S4
VSW_WLED
126
137
VDD_WLED
OVP_WLED
113
GND_WLEDI_1
114
125
GND_WLEDI_2
WLED_1
79
103
VDD_S5
VLED_FLASH
92
GND_S5
CHG_PGND
- 199 -
PCB REVISION
TOL=0.05
PCB_REVISION
R4130
100K
+1V8_VREG_L12
BACKUP BATT
+1V15_VSW_S1
+1V15_VSW_S2
10uAH / 0.03F
+1V35_VSW_S3
+2V1_VSW_S4
VCOIN
+1V15_VSW_S5
Note 8
Output capacitor should be placed close to MSM load
ground cap directly to main ground using separate via.
Main ground should be continuous (not fragmented) plane
between output capacitor and the PMIC
+1V225_VREG_L1
+1V2_VREG_L2
+1V15_VREG_L3
+1V2_VREG_L4
+1V2_VREG_L5
+1V8_VREG_L6
+1V9_VREG_L7
+1V8_VREG_L8
+2V05_VREG_L9
+1V8_VREG_L10
PMIC Internal Use for VREG_L6
Note 6
+1V8_VREG_L12
PMIC Internal Use for VREG_RF_CLK
+2V75_VREG_L14
+2V8_VREG_L15
+3V0_VREG_L16
+2V95_VREG_L17
+2V95_VREG_L18
+2V85_VREG_L19
+3V075_VREG_L20
+2V95_VREG_L21
+2V95_VREG_L22
+2V95_VREG_L23
+1V3_VREG_L24
+2V075_VREG_L25
+2V95_VREG_L28
+1V8_VREG_LVS1
L4136
10u
+VPWR
PMIC_LED_A
Up to 10EA of LED
ZD4130
PMIC_LED_C
FLASH_LED_OUT_P
C4163
4.7u
VREG_L26_L27_NOT_USE
Copyright © 2014 LG Electronics. Inc. All right reserved.
6. CIRCUIT DIAGRAM
Rev
R4130 R4131
0
100K
20K
0.300
A
100K
30K
0.415
B
100K
43K
0.541
C
100K
68K
0.729
D
100K
100K
0.900
E
100K
180K
1.157
1.0
100K
DNI
1.800
1.1
DNI
100K
0.000
C4182
47u
Only for training and service purposes
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