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During CTCSS operation, the voice signal is mixed
with the TONE ENC subaudible tone signal from pin 43
of the CPU and delivered to the RF-UNIT through jacks
J3003 and J1002. During DTMF operation, the DTMF tones
from pin 55 of the CPU are input to the IDC stage.
(3) VHF Band (145/220 MHz (USA Only)) Transmission
Modulating audio from the CNTL-UNIT passes
through deviation setting D/A converter Q3011
(M62364FP 600D) to VHF MOD of the VCO-UNIT
mounted on the RF-UNIT. This signal is applied to varac-
tor D4005 in the tank circuit of VHF VCO Q4004
(EC3H07B-TL), which oscillates at the desired VHF trans-
mitting frequency. The modulated VCO signal is buffered
by amplifier Q4006 (EC3H07B-TL ) and Q1018
(2SC5555ZD-TR) and delivered through VHF T/R diode
switch D1033 (DAN222M-T2L) to the RF-UNIT. The mod-
ulated low-level VHF transmit signal from the VCO is
passed through diode switch D1029 (DAN222M-T2L) to
amplifier Q1011 (2SC5226-5-TL). The modulated VHF
transmit signal from the VCO is amplified by Q1015
(2SK3475) and RF power amplifier Q1023 (2SK3476) up
to 5 W (depending on the power source). The RF output
passes through TX diode switch D1049. RF output is
passed by T/R switch and low-pass filter to suppress har-
monics and spurious products before output to the an-
tenna at the antenna terminal.
(4) UHF Band Transmission
Modulating audio from the CNTL-UNIT passes
through deviation setting D/A converter Q3011
(M62364FP 600D) to UHF MOD of the VCO-UNIT
mounted on the RF-UNIT. This signal is applied to varac-
tor D4002 in the tank circuit of UHF VCO Q4002
(EC3H07B-TL), which oscillates at the desired UHF trans-
mitting frequency. The modulated VCO signal is buffered
by amplifier Q4006 (EC3H07B-TL ) and Q1017
(2SC5555ZD-TR) and delivered through UHF T/R diode
switch D1035 (HN2D01FUTE85R) to the RF-UNIT. The
modulated low-level UHF transmit signal from the VCO
is passed through diode switch D1029 (DAN222M-T2L)
to amplifier Q1011 (2SC5226-5-TL). The modulated UHF
transmit signal from the VCO is amplified by Q1015
(2SK3475) and RF power amplifier Q1023 (2SK3476) up
to 5 W (depending on the power source). The RF output
Circuit Description
passes through TX diode switch D1046. RF output is
passed by T/R switch and low-pass filter to suppress har-
monics and spurious products before output to the an-
tenna at the antenna terminal.
PLL Frequency Synthesizer
PLL IC Q1020 (MB15A01PFV1-G-BND-EF) on the RF-
UNIT consists of a data shift register, reference frequency
divider, phase comparator, charge pump, intermittent
operation circuit, and band selector switch. Serial PLL data
from the CPU is converted into parallel data by the shift
register in the PLL IC and is latched into the comparative
frequency divider and reference frequency divider to set
a frequency dividing ratio for each. An 11.7 MHz refer-
ence signal produced by X1001 is input to REF pin 1 of
the PLL IC. The internal reference frequency divider di-
vides the 11.7 MHz reference by 2,050 (or 1,640) to obtain
a reference frequency of 5 kHz (or 6.25 kHz), which is
applied to the phase comparator. Meanwhile, a sample of
the output of VHF VCO Q4004 (EC3H07B-TL) or UHF
VCO Q4002 (EC3H07B-TL) on the VCO-UNIT, buffered
by Q4006 (EC3H07B-TL), is input to the PLL IC, where it
is frequency-divided by the internal comparative frequen-
cy divider to produce a comparative frequency also ap-
plied to the phase comparator. The phase comparator com-
pares the phase between the reference frequency and com-
parative frequency to output a pulse corresponding to the
phase difference between them. This pulse is input to the
charge pump, and the output from the charge pump pass-
es through a loop filter composed of L1043, C1121, R1080,
R1079, and either R1082, C1139, R1093 and C1145 for VHF,
or R1081, C1138, R1092 and C1140 for UHF, which con-
vert the pulse into a corresponding smoothed varactor
control voltage (VCV). The VCV is applied to varactor
D4004 and D4013 in the VHF VCO tank circuit, or to var-
actor D4001 in the UHF VCO tank circuit, to eliminate
phase difference between the reference frequency and
comparative frequency, and so locking the VCO oscilla-
tion frequency to the reference crystal. The VCO frequen-
cy is determined by the frequency-dividing ratio sent from
the CPU to the PLL IC. During receiver power save oper-
ation, the PLL circuit operates intermittently to reduce
current consumption, for which the intermittent opera-
tion control circuit reduces the lock-up time.
9
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